US 7,444,448 B2 · Data bus mechanism for dynamic source synchronized sampling adjust

Abstract

An integrated device for sampling data packets asserted sequentially on a system bus, including a clock input for receiving a bus clock signal, a data bus interface for receiving the data packets and for detecting at least one data strobe indicating data validity, and dynamic source synchronized sampling adjust logic. The dynamic source synchronized sampling adjust logic includes sampling logic which selects and latches each data packet in response to the data strobe and which provides latched data packets, and select logic which selects from among the latched data packets based on a read pointer. A method of sampling data packets asserted sequentially on a data bus for one or more bus clock cycles including detecting operative edges of a data strobe, selecting a data packet for each detected operative edge, and latching each selected data packet.

Claims20

Dependent claims

A dynamic source synchronized sampling adjust system for sampling a plurality of data packets distributed among a plurality of sequential data beats on a data bus during each of at least one cycle of a bus clock, wherein at least one data strobe is provided indicating validity of each of the plurality of data packets, said dynamic source synchronized sampling adjust system comprising:

a plurality of first multiplexers, each having a first input for coupling to the data bus, a second input receiving a corresponding one of a plurality of latched data packets, a select input receiving a corresponding one of a plurality of select signals, and an output;
a plurality of registers, each having an input coupled to an output of a corresponding one of said plurality of first multiplexers, an output providing a corresponding one of said plurality of latched data packets, and a clock input for receiving the at least one data strobe;
at least one second multiplexer having a plurality of inputs coupled to corresponding outputs of said plurality of registers, an output providing a selected one of said plurality of latched data packets, and a select input receiving a read pointer;
and
timing logic having at least one input for receiving the at least one data strobe and a plurality of outputs providing said plurality of select signals.

2 more elements

An integrated device for sampling a plurality of data packets asserted sequentially on a system bus during each of at least one cycle of a bus clock signal, the system bus including at least one data strobe signal indicating validity of each data packet, the device comprising:

a clock input for receiving the bus clock signal;
a data bus interface for receiving the plurality of data packets and for detecting the at least one data strobe signal;
and
dynamic source synchronized sampling adjust logic, comprising:
sampling logic, coupled to the data bus interface, which selects and latches each of the plurality of data packets in response to the at least one data strobe signal and which provides a plurality of latched data packets;
and
select logic, coupled to said sampling logic, which selects from among said plurality of latched data packets based on a read pointer.

4 more elements

Dependencies are inferred from the claim text.

Data bus mechanism for dynamic source synchronized sampling adjust

Life of this patent

Data bus mechanism for dynamic source synchronized sampling adjust

Life of this patent

Abstract

Claims20