Faster shift value calculation using modified carry-lookahead adder

#The technical field relates to an apparatus and method for use in implementing a floating point multiply-accumulate operation.

#Logic circuitry has been developed to implement a floating point multiply-accumulate operation (FMAC). This operation performs on three operands (A, B, C) the operation A*B+C. The FMAC operation is useful in that it can be used to implement both addition and multiplication in logic circuitry. In particular, for an add operation, the operand A is set to a value one. For a multiply operation, the operand C is set to a value zero.

#For example, FIG. 1 is a diagram of a prior art circuit 10 for use in implementing an FMAC operation. In circuit 10, three latches 12, 14, and 16 contain three 17-bit operands A, B, and C. The values of those operands are input to a first carry-save adder (CSA) 18. The result of the first CSA 18 is input to a second CSA 20 along with the value of a constant received on line 22. Finally, the output of the second CSA adder 20 is input to a carry-lookahead adder (CLA) 24, which performs an add operation and outputs a resulting shift value on line 26 for use in an FMAC operation.

#The accompanying drawings are incorporated in and constitute a part of this specification and, together with the description, explain the advantages and principles of the invention. In the drawings,

#FIG. 1 is a logic diagram of a prior art circuit for use in implementing an FMAC operation, including a carry-lookahead adder (CLA) 24;

#FIG. 2 is a logic diagram of a circuit for use in implementing an FMAC operation consistent with the present invention, including a CLA 40;

#Circuitry consistent with the present invention reduces propagation delays in performing an FMAC operation by eliminating one stage of logic used in generating a shift value for the operation. Another stage of logic is modified to perform a parallel logic operation and account for the reduced logic stage. This results in increased speed of execution in calculating the shift value for use in an FMAC operation.

#FIG. 2 is a logic diagram of a circuit 30 for use in performing an FMAC operation consistent with the present invention. Circuit 30 illustrates modification of prior art circuit 10 shown in FIG. 1. Circuit 30 includes three latches 32, 34, and 36 for containing three operands A, B and C for the FMAC operation, shown as 17-bit operands in this example. A CSA 38 receives the values of operands A, B, and C from latches 32, 34, and 36. In circuit 30, however, a second CSA corresponding with CSA 20 in circuit 10 is eliminated. Elimination of the second CSA increases speed of calculation of the resulting shift value for use in an FMAC operation by eliminating one stage of logic; it thus reduces the corresponding propagation delays.

#A logic block 40 receives the outputs from CSA 38 and provides a resulting shift value on line 48. The shift value is used, as explained above, to line up mantissas for the add operation. In this example, logic block 40 is implemented using a CLA that is modified to logically perform an exclusive-OR (XOR) operation on the result of the CLA operation based upon a control signal 46. The XOR function is performed on the most significant bit of the result. Control signal 46 is generated based upon whether the FMAC operation is of SIMD type or non-SIMD type; SIMD operations are known in the art. As explained below, the XOR operation can be implemented within the existing circuitry of a CLA in logic block 40 and thus does not generate any additional propagation delay.