Hardware acceleration system for logic simulation using shift register as local cache

A simulation processor for performing logic simulation of a logic design including a plurality of logic gates, the simulation processor comprising:

• an interconnect system;
• and
• a plurality of processor units communicatively coupled to each other via the interconnect system, wherein each of at least two of the processor units includes:
• a processor element configurable to simulate at least one of the logic gates;
• a shift register associated with the processor element and including a plurality of entries to store intermediate values during operation of the processor element, the shift register coupled to receive an output of the processor element;
• a local memory associated with the processor element for storing data from the simulation processor and loading data to the simulation processor;
• a first multiplexer either selecting the output of the processor element as input to the shift register or refreshing the shift register, in response to a first selection signal;
• a second multiplexer selecting one of the entries of the shift register in response to a second selection signal;
• and
• a third multiplexer selecting another one of the entries of the shift register in response to a third selection signal.

A VLIW processor for performing logic computations, comprising:

• an interconnect system;
• and
• a plurality of processor units communicatively coupled to each other via the interconnect system, wherein each of at least two of the processor units includes:
• a processor element configurable to implement at least a portion of the logic computations;
• a shift register associated with the processor element and including a plurality of entries to store intermediate values during operation of the processor element, the shift register coupled to receive an output of the processor element and also coupled to transfer intermediate values to the interconnect system;
• and
• one or more multiplexers coupled between the shift register and the interconnect system, each such multiplexer for selecting one of the entries of the shift register in response to a selection signal and further for transferring the selected entry to the interconnect system, and
• wherein the output of the processor element is coupled to the shift register without an intervening latch, and the shift register is coupled to the interconnect system with an intervening latch.