Generation of a testbench for a representation of a device

A system for generating a testbench for a representation of a device to be incorporated in a data processing apparatus, the testbench providing a test environment that represents one or more components of the data processing apparatus with which that device is to be coupled, the representation of the device being configurable based on configuration data specifying predetermined attributes of the one or more components, the system comprising:

• logic operable to read the configuration data used to configure the representation of the device;
• and
• generation logic operable to generate the testbench with reference to the configuration data and a first set of templates defining the test environment and to generate the representation of the device with reference to the configuration data and a second set of templates defining the representation of the devices,
• wherein the representation of the device is formed from constituent blocks and the second set of templates defines the representation of the device and its constituent blocks.

A method of generating a testbench for a representation of a device to be incorporated in a data processing apparatus, the testbench providing a test environment that represents one or more components of the data processing apparatus with which that device is to be coupled, the representation of the device being configurable based on configuration data specifying predetermined attributes of the one or more components, the method comprising the steps of:

• (a) receiving the configuration data used to configure the representation of the device;
• (b) generating the testbench with reference to the configuration data and a first set of templates defining the test environment;
• and
• (c) generating the representation of the device with reference to the configuration data and a second set of templates defining the representation of the device,
• wherein said device is a bus interconnect block,
• the method further comprising employing a simulation tool to run a model of the data processing apparatus using the representation of the device and the testbench,
• wherein the first set of templates includes a master template defining a master engine coupled to a bus and operable during running of the model to generate test stimuli for input via the bus to the representation of the device,
• wherein the master template includes a master monitor operable during running of the model to monitor signals on the bus to which the master engine is coupled, and
• wherein the testbench includes a scoreboard for checking data integrity within the model, and the master monitor is operable to output data to the scoreboard indicative of the signals on the bus to which the master engine is coupled.

A method of generating a testbench for a representation of a device to be incorporated in a data processing apparatus, the testbench providing a test environment that represents one or more components of the data processing apparatus with which that device is to be coupled, the representation of the device being configurable based on configuration data specifying predetermined attributes of the one or more components, the method comprising the steps of:

• (a) receiving the configuration data used to configure the representation of the device;
• (b) generating the testbench with reference to the configuration data and a first set of templates defining the test environment;
• and
• (c) generating the representation of the device with reference to the configuration data and a second set of templates defining the representation of the device,
• wherein said device is a bus interconnect block and the method further comprises the step of:
• employing a simulation tool to run a model of the data processing apparatus using the representation of the device and the testbench,
• wherein the first set of templates includes a slave template defining a slave engine coupled to a bus and operable during running of the model to generate response signals in reply to test stimuli received from the representation of the device,
• wherein the slave template includes a slave monitor operable during running of the model to monitor signals on the bus to which the slave engine is coupled, and
• wherein the testbench includes a scoreboard for checking data integrity within the model, and the slave monitor is operable to output data to the scoreboard indicative of the signals on the bus to which the slave engine is coupled.

A method of generating a testbench for a representation of a device to be incorporated in a data processing apparatus, the testbench providing a test environment that represents one or more components of the data processing apparatus with which that device is to be coupled, the representation of the device being configurable based on configuration data specifying predetermined attributes of the one or more components, the method comprising the steps of:

• (a) receiving the configuration data used to configure the representation of the device;
• (b) generating the testbench with reference to the configuration data and a first set of templates defining the test environment;
• and
• (c) generating the representation of the device with reference to the configuration data and a second set of templates defining the representation of the device,
• wherein there are a number of different component types, and the predetermined attributes specified by the configuration data indicate the component type for each of said one or more components,
• wherein said device is a bus interconnect block,
• wherein one of the component types is a master type, and for each of said one or more components which is a master type, the predetermined attributes identify connections to any slave components within said one or more components that that master type component is connected to, and
• wherein the connections are identified as either connections to a local slave component not shared with other master components, or as connections through a bus matrix of the bus interconnect block to a shared slave component shared with one or more other master components.