Execution unit for performing the data encryption standard

An execution unit adapted to perform a given round of the Data Encryption Standard, the execution unit comprising:

• a) a Left Half input;
• b) a Key input;
• c) a Table input;
• d) a first group of transistors configured to receive the Table input, perform a table look-up, and output data;
• e) a first exclusive-or operator having two inputs and an output, the first exclusive-or operator configured to receive the Left Half input and the Key input;
• f) a second exclusive-or operator having two inputs and an output, the second exclusive-or operator configured to receive the output of the first group of transistors and the output of the first exclusive-or operator;
• g) a third exclusive-or operator having two inputs and an output, the third exclusive-or operator configured to receive the Left Half input and the output of the first group of transistors;
• and
• h) a multiplexer, the multiplexer having two data inputs and an output, the first of the two data inputs configured to receive the output of the first exclusive-or operator, the second of the two data inputs configured to receive the output of the second exclusive-or operator;
• i) wherein the output of the multiplexer is used as the Table input for the next round of the Data Encryption Standard;
• and
• k) wherein the output of the third exclusive-or operator is used as a Left Half input for the next round of the Data Encryption Standard.

An execution unit adapted to perform a given round of the Data Encryption Standard, the execution unit comprising:

• a) a Left Half input;
• b) a Key input;
• c) a Table input;
• d) a Select input;
• e) a first group of transistors configured to receive the Table input, perform a table look-up, and output data;
• f) a first exclusive-or operator having two inputs and an output, the first exclusive-or operator configured to receive the Left Half input and the Key input;
• g) an AND operator, the AND operator having two inputs and an output, the first of the two inputs of the AND operator configured to receive the output of the first group of transistors, the second of the two inputs of the AND operator configured to receive the Select input;
• h) a second exclusive-or operator having two inputs and an output, the second exclusive-or operator configured to receive the output of the AND operator and the output of the first exclusive-or operator;
• and
• i) a third exclusive-or operator having two inputs and an output, the third exclusive-or operator configured to receive the Left Half input and the output of the first group of transistors;
• l) wherein the output of the second exclusive-or operator is used as the Table input for the next round of the Data Encryption Standard;
• and
• j) wherein the output of the third exclusive-or operator is used as a Left Half input for the next round of the Data Encryption Standard.

An execution unit adapted to perform a given round of the Data Encryption Standard, the execution unit comprising:

• a) a Left Half input;
• b) a Key input;
• c) a Table input;
• d) a Select input;
• e) a first group of transistors configured to receive the Table input and the Select input, perform a table look-up, and output, via a first output, the result of the table look-up, the first group of transistors further configured to output the result of the table look-up, via a second output, if the Select input is a first value, and configured to output a zero, via the second output, if the Select input is a second value;
• f) a first exclusive-or operator having two inputs and an output, the first exclusive-or operator configured to receive the Left Half input and the Key input;
• g) a second exclusive-or operator having two inputs and an output, the second exclusive-or operator configured to receive the result output via the second output of the first group of transistors and the output of the first exclusive-or operator;
• and
• h) a third exclusive-or operator having two inputs and an output, the third exclusive-or operator configured to receive the result output via the first output of the first group of transistors and the Left Half input;
• m) wherein the output of the second exclusive-or operator is used as the Table input for the next round of the Data Encryption Standard;
• and
• i) wherein the output of the third exclusive-or operator is used as a Left Half input for the next round of the Data Encryption Standard.