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US 7,443,944 B2Granted
Shift register, image display apparatus containing the same and signal generation circuit
AssigneeMitsubishi Electric Corporation
InventorsYouichi Tobita, Hiroyuki Murai
Life of this patent
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Abstract
A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.
Claims24
A shift register comprising:
- a clock terminal and an output terminal;
- a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;
- second and third transistors each configured to discharge said output terminal;
- and
- a driving circuit configured to switch between said second and third transistors for driving, on the basis of a change in level of a predetermined control signal, wherein
- nodes to which control electrodes of said first, second and third transistors are connected are defined as first, second and third nodes, respectively,
- said shift register further comprising:
- a fourth transistor having a control electrode connected to said second node and configured to discharge said first node;
- and
- a fifth transistor having a control electrode connected to said third node and configured to discharge said first node, wherein
- input of said clock signal to said clock terminal is prohibited at least for one pulse just after the change in level of said predetermined control signal.
8 more elements
An image display apparatus comprising a multistage shift register formed of a plurality of shift registers connected in cascade as a gate-line driving circuit, wherein
- each stage of said multistage shift register includes:
- a clock terminal and an output terminal;
- a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;
- second and third transistors each configured to discharge said output terminal;
- and
- a driving circuit configured to switch between said second and third transistors for driving, on the basis of a change in level of a predetermined control signal, wherein
- nodes to which control electrodes of said first, second and third transistors are connected are defined as first, second and third nodes, respectively,
- said shift register further comprising:
- a fourth transistor having a control electrode connected to said second node and configured to discharge said first node;
- and
- a fifth transistor having a control electrode connected to said third node and configured to discharge said first node, wherein
- input of said clock signal to said clock terminal is prohibited at least for one pulse just after the change in level of said predetermined control signal.
9 more elements
A shift register comprising:
- a clock terminal and an output terminal;
- a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;
- second and third transistors each configured to discharge said output terminal;
- and
- a driving circuit configured to switch between said second and third transistors for driving, on the basis of a change in level of a predetermined control signal, wherein
- nodes to which control electrodes of said first, second and third transistors are connected are defined as first, second and third nodes, respectively,
- said shift register further comprising:
- a fourth transistor having a control electrode connected to said second node and configured to discharge said first node;
- a fifth transistor having a control electrode connected to said third node and configured to discharge said first node;
- and
- a discharging element configured to discharge said first node in a predetermined time period just after the change in level of said control signal on the basis of a reset signal activated in said predetermined time period.
8 more elements
An image display apparatus comprising a multistage shift register formed of a plurality of shift registers connected in cascade as a gate-line driving circuit, wherein
- each stage of said multistage shift register includes:
- a clock terminal and an output terminal;
- a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;
- second and third transistors each configured to discharge said output terminal;
- and
- a driving circuit configured to switch between said second and third transistors for driving, on the basis of a change in level of a predetermined control signal, wherein
- nodes to which control electrodes of said first, second and third transistors are connected are defined as first, second and third nodes, respectively,
- said shift register further comprising:
- a fourth transistor having a control electrode connected to said second node and configured to discharge said first node;
- a fifth transistor having a control electrode connected to said third node and configured to discharge said first node;
- and
- a discharging element configured to discharge said first node in a predetermined time period just after the change in level of said control signal on the basis of a reset signal activated in said predetermined time period.
9 more elements
A signal generation circuit for generating a reset signal activated for a predetermined time period just after a change in level of a control signal, on the basis of said control signal composed of first and second control signals complementary to each other, and supplying said reset signal to a shift register, wherein
- said shift register includes:
- a clock terminal and an output terminal;
- a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;
- second and third transistors each configured to discharge said output terminal;
- and
- a driving circuit configured to switch between said second and third transistors for driving, on the basis of a change in level of said control signal, wherein
- nodes to which control electrodes of said first, second and third transistors are connected are defined as first, second and third nodes, respectively,
- said shift register further includes:
- a fourth transistor having a control electrode connected to said second node and configured to discharge said first node;
- a fifth transistor having a control electrode connected to said third node and configured to discharge said first node;
- and
- a discharging element configured to discharge said first node in said predetermined time period on the basis of said reset signal,
- said signal generation circuit comprising:
- a first delay circuit configured to generate a first delay signal delayed from a time at which said first control signal is activated;
- a second delay circuit configured to generate a second delay signal delayed from a time at which said second control signal is activated;
- and
- a pulse generation circuit configured to generate a pulse signal activated in accordance with activation of said first and second control signals and deactivated in accordance with activation of said first and second delay signals, wherein
- said pulse signal is output as said reset signal.
15 more elements
Dependencies are inferred from the claim text.