US 7,443,937 B2Granted

High resolution digital clock multiplier

AssigneeTexas Instruments Incorporated

InventorVivek Sarda

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Abstract

A high resolution programmable clock synthesizer that is portable across processes and, thus, process independent is disclosed herein. The clock synthesizer provides a dynamic solution, in that the frequency of the desired clock signal is programmable. Initially, a control unit monitors the input clock signal and the output clock signal to provide the appropriate control signals to a delay string buffer and a fine tuning unit based upon the desired frequency of the output clock signal. While the delay string buffer provides a coarse adjustment to the input clock signal, fine control is provided through the use of the fine tuning unit which further adjustments to the input clock signal. This clock synthesizer exceeds the accuracy of known delay line oscillators by using drive strengths of the in-loop elements to provide a better granularity for the clock synthesizer. Thereby, high resolution is achieved through the use of coarse adjustment and fine adjustment.

Claims13

Dependent claims

A clock synthesizer for generating a desired clock signal from an input clock signal, comprising:

an exclusive OR gate, having a first input, a second input and an output, the first input coupled to receive a reset signal;
a delay string buffer having an input, a control input and an output, the delay string buffer input coupled to the output of the exclusive OR gate,
wherein;
a fine tuning unit, having an input, a control input and an output, the fine tuning unit input coupled to the output of the delay string buffer, the fine tuning unit output coupled to the second input of the exclusive OR gate;
and
a control unit, having a first input, a second input and an output, the first input of the control unit coupled to receive the input clock signal and the second input of the control unit coupled to the output of the exclusive OR gate to generate a control signal at the output;
wherein the control input of the delay string buffer is coupled to receive the control signal to provide a coarse adjustment of the input clock signal corresponding to the desired clock signal, and wherein the control input of the fine tuning unit is coupled to receive the control signal to provide a fine adjustment of the input clock signal corresponding to the desired clock signal.

4 more elements

A method of synthesizing a multiplied clock signal at a desired frequency, comprising:

a. receiving an input clock signal in a clock synthesizer;
b. resetting initialization variables for a control unit within the clock synthesizer;
c. generating a coarse adjustment for a delay buffer string within the clock synthesizer;
d. setting the coarse adjustment by sending control signals from the control unit to the delay buffer string;
e. generating a fine adjustment for a fine tuning unit within the clock synthesizer;
f. setting the fine adjustment by sending control signals from the control unit to the fine tuning unit;
g. providing dither to a generated clock signal by shifting the signal modified by the fine tuning unit:
h. monitoring the frequency of the generated clock signal at predetermined intervals (R) of time per second;
i. returning to step (e) when a fine adjustment of the generated clock signal is necessary;
and
j. returning to step (h) until the system that incorporates the clock synthesizer powers down.

8 more elements

Dependencies are inferred from the claim text.