Apparatus for inputting clock signal and data signals of small amplitude level with start timing of inputting clock signal ahead of that of inputting data signals

A semiconductor apparatus comprising a plurality of units connected to each other by a cascade connection and adapted to pass a start signal therethrough, each of said units comprising:

• a shift register adapted to pass said start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals;
• a data register adapted to latch sequential data signals of the large amplitude level in synchronization with said latch signals;
• a data latch circuit adapted to latch all said sequential data signals latched in said data register in synchronization with a strobe signal;
• and
• a receiver connected to said shift register and said data register, said receiver adapted to convert differential clock signals of a small amplitude level into said clock signal of the large amplitude level from a timing of generation of said strobe signal to a timing of completion of latching all said sequential data signals in said data register, and transmit said clock signal of the large amplitude level to said shift register, and adapted to convert differential data signals of the small amplitude level into said sequential data signals from a timing of generation of said start signal to the timing of completion of latching all said sequential data signals in said data register and transmit said sequential data signals to said data register.

A receiver of a source driver, comprising:

• a first receiving circuit receiving a clock signal;
• a plurality of second receiving circuits each receiving a data signal;
• a bias circuit for producing first and second bias voltages;
• a first switch coupled between said bias circuit and said first receiving circuit and controlled by a first control signal to apply said first bias voltage to said first receiving circuit;
• and
• a second switch coupled between said bias circuit and said second receiving circuits and controlled by a second control signal different from said first control signal to apply said second bias voltage to said second receiving circuits.