Circuitry for padded communication protocols

A method of receiving and unpadding, successively received, padded blocks of data, each of the padded blocks of data including a first number of data bits that are initially received serially in a serial data signal, and each of the padded blocks being converted by the method to an unpadded block that includes a second number of data bits that is less than the first number, the method comprising:

• deriving from a reference clock signal a common signal;
• producing first and second further clock signals from the common signal;
• using the first further clock signal in at least some processing of the padded data, including using the first further clock signal to assemble in parallel from the serial data signal a group of successive data bits equal in number to the first number without regard for where in the group padding bits occur;
• and
• using the second further clock signal in at least some processing of the unpadded data, including using the second further clock signal to separate from successive ones of the groups successive unpadded blocks and to output each of said unpadded blocks in parallel, wherein the first and second further clock signals have respective, different, first second frequencies, at least one of which is different from frequency of the common signal.

Apparatus for receiving and unpadding, successively received, padded blocks of data, each of the padded blocks of data including a first number of data bits that the apparatus initially receives serially in a serial data signal, and each of the padded blocks being converted by the apparatus to an unpadded block that includes a second number of data bits that in less than the first number, the apparatus comprising:

• first circuitry adapted to derive from a reference clock signal a common signal;
• second circuitry adapted to produce first and second further clock signals from the common signal;
• third circuitry adapted to use the first further clock signal in at least some processing of the padded data, including using the first further clock signal to assemble in parallel from the serial data signal a group of successive data bits equal in number to the first number without regard for where in the group padding bits occur;
• and
• fourth circuitry adapted to use the second further clock signal in at least some processing of the unpadded data, including using the second further clock signal to separate from successive ones of the groups successive unpadded blocks and to output each of said unpadded blocks in parallel, wherein the first and second further clock signals have respective, different, first and second frequencies, at least one of which is different from frequency of the common signal.