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US 7,443,911 B2Granted
Communication devices capable of using system clock inputs for embedded television applications
AssigneeSilicon Laboratories Inc.
InventorsShahram Tadayyon, James M. Nohrden, James Ting-Yu Kao
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Abstract
According to one embodiment of the present invention, a device may receive one of multiple frequencies at a clock input of the device; determine which of the multiple frequencies is received; and generate at least one internal clock frequency for operation of the device using the received frequency. For example, such a device may be embedded within a system having a receiver to receive a satellite signal spectrum and to tune a signal channel and baseband circuitry coupled to the receiver to process digital data corresponding to the signal channel, where the baseband circuitry operates at the frequency provided to the device.
Claims18
An apparatus comprising:
- a communication device having a first pin to receive a system clock frequency of a system and a second pin which, in connection with the first pin, is to receive a reference clock frequency or a system clock frequency from a crystal oscillator coupled to the communication device;
- a clock interface coupled to the first and second pins to receive the system clock frequency or the reference clock frequency;
- a phase-locked loop coupled to the clock interface to provide a plurality of internal clocks to drive multiple components of the communication device from the system clock frequency or the reference clock frequency;
- logic coupled to the phase-locked loop to control the phase-locked loop based on which one of the system clock frequency and the reference clock frequency is input into the communication device, wherein the logic is coupled to receive and analyze a clock selection input signal received in the apparatus during a first portion of a power on or reset state of the apparatus and to exclusively select the system clock frequency or the reference clock frequency based on a value of the clock selection input signal;
- and
- wherein an interconnect of the communication device is shared between the clock selection input signal and an output logic signal;
- and a driver is coupled to the interconnect, wherein the logic is to cause an output of the driver into a high-impedance state during the power on or reset state.
4 more elements
A modem comprising:
- a clock generation circuit to generate at least one internal clock frequency exclusively selecting a first frequency or a second frequency obtained via a clock input, responsive to a control signal received during a power on or reset state via a second input of the modem;
- wherein said control signal is indicative of which of the first frequency and the second frequency is input into the clock generation circuit, the first frequency corresponding to a system clock signal of a video device and the second frequency corresponding to a crystal frequency;
- a frequency selection logic coupled to the clock generation circuit to indicate which of the first frequency or the second frequency is input to said clock input, responsive to said control signal;
- and
- a driver coupled to the second input to provide a logic output signal after the control signal is received, wherein an output of the driver is placed into a high-impedance state during the power on or reset state by said logic.
2 more elements
A system comprising:
- a receiver to receive a satellite signal spectrum and to tune a signal channel;
- baseband circuitry coupled to the receiver to process digital data corresponding to the signal channel, the baseband circuitry to operate at a system clock frequency;
- and
- a communication device coupled to the baseband circuitry having a clock generation circuit including a clock interface to receive the system clock frequency or a second clock frequency on a common pin, the clock generation circuit further including a phase-locked loop coupled to the clock interface to generate a plurality of internal clocks each at a fixed frequency regardless of whether the second clock frequency or the system clock frequency is received, the plurality of internal clocks to drive multiple components of the communication device, logic coupled to the phase-locked loop to exclusively select the system clock frequency or the second clock frequency for use in the communication device based on a control signal received on an interconnect, and a driver coupled to the interconnect, wherein the logic is to cause an output of the driver into a high-impedance state during a power on or reset state, and the driver is to thereafter output a data carrier detect signal.
1 more element
Dependencies are inferred from the claim text.