Apparatus and method for spread spectrum clock generator with accumulator
AssigneeNational Semiconductor Corporation
InventorsWilliam Llewellyn, Ha Chu Vu
Life of this patent
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Abstract
A method and apparatus for spread spectrum clock generation is provided. Modulation of the clock signal may be accomplished with an N/N−1 clock divider. The N/N−1 clock divider is configured to divide the clock signal by N or N−1, depending on the carry output signal of an accumulator circuit. The accumulator circuit is configured to provide the carry output signal in response to a modulating waveform signal. The modulating waveform signal may be a triangle wave, a sinusoidal wave, another waveform appropriate for spread-spectrum clock generation, and the like.
Claims20
A circuit for spread spectrum clock generation, comprising:
- a spread spectrum clock generator that is arranged to provide an output clock signal, wherein the spread spectrum clock generator is arranged such that the output clock signal is a clock signal that is a spread-spectrum signal, and wherein the spread spectrum clock generator includes:
- a phase detection circuit that is configured to provide an error signal from a reference signal and a feedback signal;
- a voltage controlled oscillator circuit that is configured to provide a synthesized signal from the error signal, wherein the synthesized signal is a clock signal, and wherein the output clock signal is based, at least in part, on the synthesized signal;
- a modulating waveform generator circuit that is configured to provide a modulating waveform signal that varies over time as a modulating waveform;
- an accumulator circuit that is configured to provide a carry signal from the modulating waveform signal;
- and
- an adjustable clock divider circuit that is configured to provide an adjustable clock divider output signal from an adjustable clock divider input signal, wherein the adjustable clock divider input signal is based at least in part on the synthesized signal, the feedback signal is based at least in part on the adjustable clock divider output signal, and wherein the adjustable clock divider circuit is configured to provide the adjustable clock divider output signal such that a frequency that is associated with the adjustable clock divider signal corresponds to the frequency associated with the adjustable clock divider input signal divided by:
- a first number, if the carry signal is associated with a first logic level, and
- a second number, if the carry signal is associated with a second logic level.
A circuit for spread spectrum clock generation, comprising:
- a phase detection circuit that is configured to provide an error signal from a reference signal and a feedback signal;
- a voltage controlled oscillator circuit that is configured to provide a synthesized signal from the error signal;
- a modulating waveform generator circuit that is configured to provide a modulating waveform signal that varies over time as a modulating waveform;
- an accumulator circuit that is configured to provide a carry signal from the modulating waveform signal;
- an adjustable clock divider circuit that is configured to provide an adjustable clock divider output signal from an adjustable clock divider input signal, wherein the adjustable clock divider input signal is based at least in part on the synthesized signal, the feedback signal is based at least in part on the adjustable clock divider output signal, and wherein the adjustable clock divider circuit is configured to provide the adjustable clock divider output signal such that a frequency that is associated with the adjustable clock divider signal corresponds to the frequency associated with the adjustable clock divider input signal divided by:
- a first number, if the carry signal is associated with a first logic level, and
- a second number, if the carry signal is associated with a second logic level;
- and
- a clock divider circuit that is configured to provide an output clock signal from the synthesized signal.
A circuit for spread spectrum clock generation, comprising:
- a phase detection circuit that is configured to provide an error signal from a reference signal and a feedback signal;
- a voltage controlled oscillator circuit that is configured to provide a synthesized signal from the error signal;
- a modulating waveform generator circuit that is configured to provide a modulating waveform signal that varies over time as a modulating waveform;
- an accumulator circuit that is configured to provide a carry signal from the modulating waveform signal;
- and
- an adjustable clock divider circuit that is configured to provide an adjustable clock divider output signal from an adjustable clock divider input signal, wherein the adjustable clock divider input signal is based at least in part on the synthesized signal, the feedback signal is based at least in part on the adjustable clock divider output signal, and wherein the adjustable clock divider circuit is configured to provide the adjustable clock divider output signal such that a frequency that is associated with the adjustable clock divider signal corresponds to the frequency associated with the adjustable clock divider input signal divided by:
- a first number, if the carry signal is associated with a first logic level, and
- a second number, if the carry signal is associated with a second logic level, wherein the accumulator circuit includes a digital adder circuit having first and second inputs, a sum output, and a carry output, wherein the digital adder circuit is arranged to receive the modulated waveform signal at the first input, the sum output is coupled to the second input, and wherein the digital adder circuit is configured to provide the carry signal at the carry output.
A circuit for spread spectrum clock generation, comprising:
- a phase detection circuit that is configured to provide an error signal from a reference signal and a feedback signal;
- a voltage controlled oscillator circuit that is configured to provide a synthesized signal from the error signal;
- a modulating waveform generator circuit that is configured to provide a modulating waveform signal that varies over time as a modulating waveform;
- an accumulator circuit that is configured to provide a carry signal from the modulating waveform signal;
- and
- an adjustable clock divider circuit that is configured to provide an adjustable clock divider output signal from an adjustable clock divider input signal, wherein the adjustable clock divider input signal is based at least in part on the synthesized signal, the feedback signal is based at least in part on the adjustable clock divider output signal, and wherein the adjustable clock divider circuit is configured to provide the adjustable clock divider output signal such that a frequency that is associated with the adjustable clock divider signal corresponds to the frequency associated with the adjustable clock divider input signal divided by:
- a first number, if the carry signal is associated with a first logic level, and
- a second number, if the carry signal is associated with a second logic level, wherein the modulating waveform is suitable for spreading a frequency spectrum that is associated with the synthesized signal relative to a frequency spectrum that is associated with the reference signal according to a down-spread modulation, and wherein the down-spread modulation is between approximately −0.5% to −1.5%.
A circuit for spread spectrum clock generation, comprising:
- a spread spectrum clock generator that is arranged to provide an output clock signal, wherein the spread spectrum clock generator is arranged such that the output clock signal is a clock signal that is a spread-spectrum signal, and wherein the spread spectrum clock generator includes:
- a phase detection circuit that is configured to provide an error signal from a phase detection input signal and a feedback signal;
- a voltage controlled oscillator circuit that is configured to provide a synthesized signal from the error signal, wherein the feedback signal is based at least in part on the synthesized signal, wherein the synthesized signal is a clock signal, and wherein the output clock signal is based, at least in part, on the synthesized signal;
- a modulating waveform generator circuit that is configured to provide a modulating waveform signal that varies over time as a modulating waveform;
- an accumulator circuit that is configured to provide a carry signal from the modulating waveform signal;
- and
- an adjustable clock divider circuit that is configured to provide an adjustable clock divider output signal from an adjustable clock divider input signal, wherein the adjustable clock divider input signal is based at least in part on a reference signal, the phase detection input signal is based at least in part on the adjustable clock divider output signal, and wherein the adjustable clock divider circuit is configured to provide the adjustable clock divider output signal such that a frequency that is associated with the adjustable clock divider signal corresponds to the frequency associated with the adjustable clock divider input signal divided by:
- a first number, if the carry signal is associated with a first logic level, and
- a second number, if the carry signal is associated with a second logic level.
A circuit for spread spectrum clock generation, comprising:
- means for determining a phase difference between a reference signal and a feedback signal;
- means for providing a synthesized signal from the determined phase difference, wherein the synthesized signal is a clock signal;
- means for providing modulating waveform signal that includes a multiple-bit digital word that varies over time as a modulating waveform;
- means for providing a carry signal from the modulating waveform signal such that a frequency of pulses in a logical level that is associated with the carry signal is determined according to a value that is associated with the multiple-bit digital word;
- means for frequency division by a first number if the carry signal is associated with a first logic level;
- and
- means for frequency division by a second number if the carry signal is associated with a second logic level.
Dependencies are inferred from the claim text.