Multi-stage multiplexing chip set having switchable forward/reverse clock relationship

An upstream multiplexing integrated circuit within a multi-stage bit stream multiplexer that operates with a switchable forward/reverse lock relationship with a downstream multiplexing integrated circuit, comprising:

• a plurality of input ports operable to receive a first plurality of bit streams at a first bit rate;
• a plurality of output ports to output a second plurality of bit streams at a second bit rate, wherein the first plurality of bit streams is greater in number than the second plurality of bit streams are in number, and wherein the first bit rate is less than the second bit rate;
• a clock circuit that generates a forward transmit clock signal for use by the upstream multiplexing integrated circuit in producing the second plurality of bit streams based upon a reference clock signal selectable from a plurality of inputs, wherein said inputs include a reverse transmit clock generated by the downstream integrated circuit;
• and
• a phase locked loop (PLL) that receives the reference clock signal and produces a PLL Data Clock having a frequency equal to the second bit rate, wherein a plurality of latches receive the PLL Data Clock, latch data multiplexed from the first bit streams and produce the plurality of second bit streams.

A method of multiplexing a first plurality of bit streams to at least one high-speed bit stream with a multistage multiplexer, comprising:

• receiving the first plurality of bit streams at a first stage multiplexing integrated circuit at a first bit rate;
• multiplexing the first plurality of bit streams into a second plurality of bit streams at a second bit rate, wherein the second bit rate exceeds the first bit rate;
• receiving the second plurality of bit streams at a second stage multiplexing integrated circuit at a second bit rate, wherein the second plurality of bit streams are fewer in number than the first plurality of bit streams is in number;
• multiplexing the second plurality of bit streams into the at least one high-speed bit stream having a line bit rate that exceeds the second bit rate:
• generating a forward transmit clock from a reference clock signal selectable from a plurality of inputs, wherein the plurality of inputs include a reverse transmit clock generated by the second stage multiplexing integrated circuit;
• and
• producing from the reference clock signal a Phase Locked Loop (PLL) Data Clock having a frequency equal to the second bit rate with a PLL, wherein a plurality of latches receive the PLL Data Clock, latch multiplexed data from the first bit streams, and produce the plurality of second bit streams.

A method of multiplexing a first plurality of bit streams to at least one high-speed bit stream with a multistage multiplexer, comprises:

• receiving the first plurality of bit streams at a first stage multiplexing integrated circuit at a first bit rate;
• multiplexing the first plurality of bit streams into a second plurality of bit streams at a second bit rate;
• receiving the second plurality of bit streams at a second stage multiplexing integrated circuit at a second bit rate, wherein the second plurality of bit streams are fewer in number than the first plurality of bit streams are in number, and wherein the first bit rate is less than the second bit rate;
• multiplexing the second plurality of bit streams into the at least one high-speed bit streams at a line bit rate that exceeds the second bit rate;
• generating a forward transmit clock from a reference clock signal selectable from a plurality of inputs, wherein the plurality of inputs include a reverse transmit clock generated by the second stage multiplexing integrated circuit;
• and
• producing a lock detect signal to indicate when a PLL is locked to the reference clock signal, wherein the reverse transmit clock is selected as the reference clock signal when the PLL is not locked to the reference clock.

A method of multiplexing a first plurality of bit streams to at least one high-speed bit stream with a multistage multiplexer, comprising:

• receiving the first plurality of bit streams at a first stage multiplexing integrated circuit at a first bit rate;
• multiplexing the first plurality of bit streams into a second plurality of bit streams at a second bit rate, wherein the second bit rate exceeds the first bit rate;
• receiving the second plurality of bit streams at a second stage multiplexing integrated circuit at a second bit rate, wherein the second plurality of bit streams are fewer in number than the first plurality of bit streams is in number;
• multiplexing the second plurality of bit streams into the at least one high-speed bit stream having a line bit rate that exceeds the second bit rate;
• generating a forward transmit clock from a reference clock signal selectable from a plurality of inputs, wherein the plurality of inputs include a reverse transmit clock generated by the second stage multiplexing integrated circuit;
• and
• producing a lock detect signal to indicate when a PLL is locked to the reference clock signal, wherein a reverse transmit clock is selected as the reference clock signal when the PLL is not locked to the reference clock.