US 7,443,888 B2Granted

Transparent sub-wavelength network

AssigneeCiena Corporation

InventorSteven A. Surek

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Abstract

An arrangement that allows transmission of client signals with higher clock fidelity is achieved by developing a phase offset measure at an ingress node, communicating it to the egress node, and recovering the client's clock from the received data and from the received phase-offset information. The ability to recover the client's clock with high fidelity is enhanced by adaptive pointer processing in intermediate nodes and the egress node of the network that the client's signal traverses. The adaptive pointer processing filters incoming pointers from upstream nodes and injects new positive and negative pointer justifications in excess of what is minimally necessary to allow them to be filtered by successive nodes and insure proper transmission over a network that employs a protocol involving framing layer frames embedded in communication layer frames. Illustratively, the network protocol is an extended ITU Recommendation G.709 Digital Wrapper protocol, arranged to employ frames of 15240 columns by four rows.

Claims30

Dependent claims

A method for communicating over a network comprising the steps of:

at an ingress node of said network, accepting a client signal arriving synchronized to a client-signal clock;
synchronizing said client signal to a processing clock of said ingress node while forming framing layer frames into which said client signal is inserted;
developing measures of phase-offset between said client signal clock and said processing clock of said ingress node;
developing an output signal of said ingress node comprising said framing layer frames and said measures;
communicating said output signal to an egress node of said network;
at said egress node, extracting said client signal from framing layer frames of said egress node;
developing a client clock from said extracted client data and from phase-offset measure obtained from said framing layer frames of said egress node;
and
outputting said extracted client data with the developed client clock;
wherein each of said ingress nodes and said egress node comprise:
a buffer responsive to an applied client signal;
a write address counter responsive to said applied client clock, developing a write address that specifies locations into which said applied client signal is written;
a processor;
a read address counter responsive to a clock provided by said processor that specifies locations from which said applied client signal is read;
a subtractor for developing a difference signal between the addresses of said write address counter and said read address counter, applying said difference signal to said processor;
and
said processor for obtaining samples related to said difference signal to serve as phase-offset signals;
where said processor develops framing layer frames that contain data retrieved by said processor from said buffer, under influence of said read address counter in a payload portion of said framing layer frames, and contain-said phase-offset signals in overhead portion of said framing layer frames.

15 more elements

A method for communicating over a network that employs framing layer frames that are inserted into payload sections of communication layer frames, the improvement comprising:

a process in an ingress node of said network that operates on a clock of an applied client signal and a native clock of said ingress node to develop a phase-offset measure that is communicated to an egress node;
and
a process in said egress node that employs received phase-offset measures to create a clock with which to output a received facsimile of said applied client signal;
wherein each of said ingress nodes and said egress node comprise:
a buffer responsive to said applied client signal;
a write address counter responsive to said applied client clock, developing a write address that specifies locations into which said applied client signal is written;
a processor;
a read address counter responsive to a clock provided by said processor that specifies locations from which said applied client signal is read;
a subtractor for developing a difference signal between the addresses of said write address counter and said read address counter, applying said difference signal to said processor;
and
said processor for obtaining samples related to said difference signal to serve as phase-offset signals;
where said processor develops framing layer frames that contain data retrieved by said processor from said buffer, under influence of said read address counter in a payload portion of said framing layer frames, and contain-said phase-offset signals in overhead portion of said framing layer frames.

9 more elements

A fiber network that includes nodes interconnected by links, where at least some of the nodes comprise circuitry that generates and operates with information that combines to allow creation of a clock at nodes of said network that operate as egress nodes that meet the requirements of the OC-N Reference Mask of the SONET standard for N less 48, and where at least one of said nodes comprises:

a buffer responsive to an applied client signal;
a write address counter responsive to an applied client clock, developing a write address that specifies locations into which said applied client signal is written;
a processor;
a read address counter responsive to a clock provided by said processor that specifies locations from which said applied client signal is read;
a subtractor for developing a difference signal between the addresses of said write address counter and said read address counter, applying said difference signal to said processor;
and
said processor for obtaining samples related to said difference signal to serve as phase-offset signals;
where said processor develops framing layer frames that contain data retrieved by said processor from said buffer, under influence of said read address counter in a payload portion of said framing layer frames, and contain-said phase-offset signals in overhead portion of said framing layer frames.

5 more elements

A network node comprising:

a buffer responsive to applied communication layer signal frames;
a clock recovery element responsive to said applied signal that develops an estimate of the rate at which bits of said frames appear in said applied signal;
a processor, responsive to said applied signal and to said clock for developing a gated clock that corresponds to payload portions of said frames, when said applied signal contains data, and for extracting pointer information from the overhead portion of said applied signal;
a write address counter responsive to said gated clock for specifying locations at which data of said applied signal is written, developing a write address that specifies locations into which said applied client signal is written;
a processor that develops a read clock and pointer justification information;
a read counter address responsive to said read clock for specifying addresses of said buffer from which data is retrieved;
combining circuitry responsive to said write address counter and to said read address counter for developing a control signal;
and
pointer processing circuitry responsive to said control signal for developing a signal that is applied to said processor.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/895,007Filed 20 Jul 2004 · us provisional application
Priority: 2 Oct 2003
Published: US 2005/0074032 A17 Apr 2005
Granted: 28 Oct 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H04J 3/0647
Clock or time synchronisation among nodes; Internode synchronisation: synchronisation among TDM nodes
H04J 3/1611
Fixed allocated frame structures: synchronous digital hierarchy [SDH] or SONET
H04J
Multiplex communication