Processor with dynamic table-based scheduling using linked transmission elements for handling transmission request collisions

A processor comprising:

• scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements;
• and
• traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements;
• wherein the scheduling circuitry is configured for utilization of at least one time slot table, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot and being configured to store at least one entry, the scheduling circuitry being operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry in the presence of collisions between request from the transmission elements for each of one or more of the time slots, through the use of a linking of colliding transmission elements and by moving at least one entry from a first location within the at least one time slot table to a second location within the at least one time slot table;
• and
• wherein the scheduling circuitry maintains a set of pointers for the time slot table, the set of pointers comprising one or more of:
• a current pointer pointing to the next location in the time slot table for which a data block will be transmitted;
• an actual pointer pointing to the location in the time slot table corresponding to actual time;
• and
• a free pointer pointing to the next location in the time slot table that is a free entry with no requesting transmission element assigned thereto.

A processor comprising:

• scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements;
• and
• traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements;
• wherein the scheduling circuitry is configured for utilization of at least one time slot table, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot, the scheduling circuitry being operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry in the presence of collisions between requests from the transmission elements for each of one or more of the time slots, through the use of a linking of colliding transmission elements;
• and
• wherein the scheduling circuitry maintains a set of pointers for the time slot table, the set of pointers comprising one or more of:
• an actual pointer pointing to the location in the time slot table corresponding to actual time;
• and
• a free pointer pointing to the next location in the time slot table that is a free entry with no requesting transmission element assigned thereto;
• and
• wherein if the free pointer and the actual pointer point to different locations in the time slot table, and the actual pointer points to a location having a valid transmission element associated therewith, an identifier of that element is written to the location in the time slot table pointed to by the free pointer, and the identifier of that element is deleted from the location in the time slot table pointed to by the actual pointer, and both the free pointer and the actual pointer are incremented by one.

A processor comprising:

• scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements;
• and
• traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements;
• wherein the scheduling circuitry is configured for utilization of at least one time slot table, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot, the scheduling circuitry being operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry in the presence of collisions between requests from the transmission elements for each of one or more of the time slots, through the use of a linking of colliding transmission elements;
• and
• wherein the scheduling circuitry maintains a set of pointers for the time slot table, the set of pointers comprising one or more of:
• a current pointer pointing to the next location in the time slot table for which a data block will be transmitted;
• an actual pointer pointing to the location in the time slot table corresponding to actual time;
• and
• a free pointer pointing to the next location in the time slot table that is a free entry with no requesting transmission element assigned thereto;
• and
• wherein a given requesting transmission element is assigned to a location in the time slot table in accordance with the following equation:
• Assigned Time Slot =AP- (FP-CP) +Requested Time Slot Interval,
• where AP denotes the actual pointer, FP denotes the free pointer, CP denotes the current pointer, and the requested time slot interval is the time slot interval requested by the requesting transmission element, such that when the actual pointer, free pointer and current pointer each point to the same location in the time slot table, the assigned time slot corresponds to the requested time slot interval.