Selective error correction for ad hoc networks having multiple communication modes

A communication device for an ad hoc network having an asynchronous communication mode and a synchronous communication mode, the device comprising:

• a receiver configured to receive a packet including a header and a payload, the header including a header error check (HEC) computed based on the header;
• an error detect circuit configured to calculate an error indicator based on the received header;
• an error correction circuit configured to modify the header based on an error correction table when the calculated error indicator corresponds to a value in the error correction table, the error correction circuit being configured to modify the header only in the synchronous communication mode;
• and
• a payload processing circuit configured to forward the received payload when the calculated error indicator indicates an error free header and/or when the error correction circuit modifies the header and to detect a received packet error when the calculated error indicator indicates an error in the header and the calculated error indicator does not correspond to a value in the error correction table in the synchronous communication mode and to detect a received packet error in the asynchronous communication mode when the calculated error indicator indicates an error in the header.