Synchronization circuit for a write operation on a semiconductor memory
AssigneeQimonda AG
InventorStefan Dietrich
Life of this patent
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Abstract
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.
Claims17
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprising:
- a controllable first FIFO clocked by a data strobe write clock control signal (WDQS signal) and storing write data on the basis of one or more successive write commands;
- a controllable second FIFO clocked by an internal clock signal and storing, for a write operation, only addresses associated with valid write data of said write data stored in said first FIFO;
- and
- a first control circuit for controlling said first FIFO;
- said first control circuit being clocked by said WDQS signal and utilizing said WDQS signal to generate an input pointer indicating at what location in said first FIFO said write data are to be buffer-stored.
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprising:
- a controllable first FIFO clocked by a data strobe write clock control signal (WDQS signal) and storing write data on the basis of one or more successive write commands;
- a controllable second FIFO clocked by an internal clock signal and storing, for a write operation, only addresses associated with valid write data of said write data stored in said first FIFO;
- and
- said first FIFO comprises a plurality of FIFO cells;
- wherein a first half of said FIFO cells are provided for storing said write data latched in response to a falling edge of said WDQS signal and a second half of said FIFO cells are provided for storing said write data latched in response to a rising edge of said WDQS signal.
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprising:
- a controllable first FIFO clocked by a data strobe write clock control signal (WDQS signal) and storing write data on the basis of one or more successive write commands;
- a controllable second FIFO clocked by an internal clock signal and storing, for a write operation, only addresses associated with valid write data of said write data stored in said first FIFO;
- and
- a control circuit for controlling said second FIFO;
- said control circuit being clocked by said internal clock signal and utilizing said internal clock signal and said write commands to generate an output pointer for said first FIFO;
- said output pointer indicating at what location in said first FIFO said valid write data are to be stored.
Dependencies are inferred from the claim text.