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US 7,443,761 B2Granted
Loop filtering for fast PLL locking
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
Estimating the term…
Abstract
Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes locking a DLL voltage while applying the control voltage of the DLL path to the loop filter of the DLL path. The method also includes transferring the control voltage from the loop filter of the DLL path to a loop filter of the PLL path after the DLL voltage locks.
Claims59
A method of locking a PLL comprising:
- locking a DLL path while applying a control voltage of the DLL path to a loop filter of the DLL path;
- locking a DLL voltage while applying the control voltage of the DLL path to the loop filter of the DLL path;
- and
- transferring the control voltage from the loop filter of the DLL path to a loop filter of the PLL path after the DLL voltage locks.
1 more element
A method of locking a DLL voltage comprising:
- generating a control voltage from a charge pump of the DLL path, while the DLL voltage locks;
- applying the control voltage to a loop filter of the DLL path;
- and
- adjusting an internal voltage in a loop filter of a PLL path towards the control voltage while applying the control voltage to the loop filter of the DLL path.
1 more element
A method of locking a PLL, comprising:
- applying a current mirror output to a PLL loop filter of a PLL path while a DLL path locks;
- transferring an output of a charge pump circuit of the DLL path from a DLL loop filter of the DLL path to the PLL loop filter of the PLL path, after the DLL path locks;
- and
- applying the output of the charge pump circuit of the DLL path to the PLL loop filter while the DLL path relocks.
1 more element
A method of locking a PLL, comprising:
- transmitting a feedback signal of a DLL path and a reference signal for the DLL path to a phase frequency detector, through a multiplexer;
- locking the DLL path by using a phase difference between the feedback signal of the DLL path and the reference signal of the DLL path detected by the phase frequency detector;
- relocking the DLL path by using a filtered signal from a PLL loop filter of a PLL path;
- transmitting a feedback signal of the PLL path and a reference signal for the PLL path to the phase frequency detector, through the multiplexer;
- and
- locking the PLL path by using a phase difference between the feedback signal of the PLL path and the reference signal of the PLL path detected by the phase frequency detector.
3 more elements
A circuit comprising:
- a DLL path including a phase frequency detector circuit, a charge pump circuit, a loop filter circuit, a bias generator, and a VCDL;
- a PLL path including the phase frequency detector circuit, the charge pump circuit, the loop filter circuit, the bias generator, and a VCO;
- and
- wherein the loop filter circuit includes:
- a DLL loop filter;
- a PLL loop filter;
- and
- a loop filter charge pump with a loop filter charge pump output connected to the PLL loop filter.
5 more elements
A loop filter circuit comprising:
- a DLL loop filter configured to receive a control voltage from a DLL path through a first switch;
- a PLL loop filter configured to receive the control voltage from a PLL path through a second switch;
- and
- a comparator configured to transmit a comparator output signal by using a difference between the control voltage from the DLL path and an internal voltage from the PLL loop filter.
1 more element
A circuit comprising:
- a DLL path including a phase frequency detector circuit, a charge pump circuit, a loop filter circuit, a bias generator, and a VCDL;
- a PLL path including the phase frequency detector circuit, the charge pump circuit, the loop filter circuit, the bias generator, and a VCO;
- wherein the phase frequency detector circuit includes:
- a multiplexer;
- a DLL lock detector;
- and
- a DLL relock detector;
- and
- wherein the loop filter circuit includes:
- a DLL loop filter switchably connected to an output from the charge pump circuit;
- and
- a PLL loop filter switchably connected to an output from the charge pump circuit.
9 more elements
A phase frequency detector circuit, comprising
- a multiplexer configured to receive a feedback signal from a VCDL of a DLL path, a reference signal for the DLL path, a feedback signal from a VCO of a PLL path, and a reference signal for the PLL path;
- a phase frequency detector;
- a DLL lock detector configured to transmit a DLL lock signal to the multiplexer and a loop filter circuit shared by the DLL path and the PLL path;
- and
- a DLL relock detector configured to transmit a DLL relock signal to the multiplexer, the VCDL of the DLL path, and the VCO of the PLL path.
2 more elements
A loop filter circuit, comprising:
- a DLL loop filter configured to receive a control voltage from a DLL path though a first switch;
- a PLL loop filter configured to receive the control voltage from the DLL path through a second switch;
- and
- a current mirror configured to charge the PLL loop filter.
1 more element
A memory device, comprising:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a synchronization circuit, the synchronization circuit including:
- a DLL path including a phase frequency detector circuit, a charge pump circuit, a loop filter circuit, a bias generator, and a VCDL;
- a PLL path including the phase frequency detector circuit, the charge pump circuit, the loop filter circuit, the bias generator, and a VCO;
- wherein the loop filter circuit includes a DLL loop filter, a PLL loop filter, a controller, and a loop filter charge pump, wherein the loop filter charge pump is configured to provide a loop filter charge pump output to the PLL loop filter;
- and
- wherein the controller is configured to transmit a DLL voltage lock signal to the phase frequency detector circuit when an internal voltage of the PLL loop filter is substantially equal a control voltage output of the charge pump circuit.
7 more elements
A memory device, comprising:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a synchronization circuit, the synchronization circuit including:
- a DLL path including a phase frequency detector circuit, a charge pump circuit, a loop filter circuit, a bias generator, and a VCDL;
- a PLL path including the phase frequency detector circuit, the charge pump circuit, the loop filter circuit, the bias generator, and a VCO;
- and
- wherein the phase frequency detector circuit includes a DLL lock detector, a DLL relock detector, a multiplexer configured to transmit signals to a phase frequency detector, and the phase frequency detector configured to transmit a signal to the charge pump circuit.
6 more elements
A processor based system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and data output devices;
- and
- a memory device coupled to the processor, wherein the memory device includes:
- a memory array;
- a row decoder coupled to the memory array,
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a synchronization circuit, the synchronization circuit including:
- a DLL path, including a VCDL;
- a PLL path, including a VCO;
- and
- a loop filter circuit, shared by the DLL path and the PLL path, and configured to transfer a control voltage from a loop filter of the DLL path to a loop filter of the PLL path, after DLL voltage lock.
11 more elements
A processor based system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and data output devices;
- and
- a memory device coupled to the processor, wherein the memory device includes:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to to-the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a synchronization circuit, the synchronization circuit including:
- a DLL path configured to filter a charge pump circuit output with a DLL loop filter while locking and configured to filter the charge pump output circuit with a loop filter of a PLL path while relocking;
- the PLL path;
- and
- a phase frequency detector circuit:
- shared by the DLL path and the PLL path;
- configured to detect a phase difference for the DLL path while the DLL path is locking and to detect a phase difference for the DLL path while the DLL path is relocking;
- and
- configured to detect a phase difference for the PLL path after the DLL path is relocked.
15 more elements
Dependencies are inferred from the claim text.