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US 7,443,756 B2Granted
Memory device having redundancy fuse blocks arranged for testing
AssigneeSamsung Electronics Co., Ltd.
InventorsYu-Lim Lee, Sung-Hoon Kim
Life of this patent
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Abstract
A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may be alternately arranged in an X-axis direction or a Y-axis direction of a wafer. Accordingly, a tester may repair defective rows or columns of the two banks without shifting from one axis.
Claims20
A memory device comprising:
- a first bank comprising first rows and first columns of a plurality of first memory cells;
- a second bank comprising second rows and second columns of a plurality of second memory cells;
- a redundancy cell block in which a plurality of redundancy cells are arranged;
- a decoder shared by the first and second banks to address the first and second memory cells;
- redundancy fuse blocks for the first bank included in the decoder to repair a defective one of the first memory cells with a first corresponding redundancy cell;
- and
- redundancy fuse blocks for the second bank included in the decoder and repair a defective one of the second memory cells with a second corresponding redundancy cell;
- wherein the redundancy fuse blocks for the first bank and the redundancy fuse blocks for the second bank are alternately arranged in the decoder.
5 more elements
A method comprising:
- interposing a decoder between first and second banks of a memory device;
- arranging redundancy fuse blocks for the first bank to repair a defective memory cell of the first bank with a first corresponding redundancy cell, in the decoder;
- and
- alternately arranging redundancy fuse blocks for the second bank to repair a defective memory cell of the second bank with a second corresponding redundancy cell, between the redundancy fuse blocks for the first bank in the decoder.
1 more element
A memory device comprising:
- a first bank of first memory cells;
- a second bank of second memory cells;
- a block of redundancy cells;
- and
- a decoder arranged between the first and second banks to access the first and second memory cells;
- wherein the decoder comprises a first redundancy fuse box to repair a defective one of the first memory cells with one of the redundancy cells, and a second redundancy fuse box to repair a defective one of the second memory cells with one of the redundancy cells;
- and
- wherein the first and second redundancy fuse boxes are arranged so that defective memory cells of the first bank and the second bank may be repaired by moving a tester in a first direction.
5 more elements
Dependencies are inferred from the claim text.