Programmable sense amplifier multiplexer circuit with dynamic latching mode
AssigneeQimonda North American Corp.
InventorsChristopher Miller, Michael Killian
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Abstract
Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.
Claims21
A method in a semiconductor memory device for controlling connection of a sense amplifier to, and disconnection from, first and second memory array segments, respectively, comprising:
- (a) in a programmable isolation mode, controlling a first switch or a second switch to disconnect the sense amplifier either from the first memory array segment or from the second memory array segment, respectively, when the first memory array or second memory array segment, respectively, is unselected and has a leakage anomaly;
- and
- (b) in a dynamic latch mode, controlling the first switch and the second switch to be in a fixed state while the first or second memory array segment, respectively, is being accessed when refreshing cells in the first or second memory array segment by cycling accesses through wordlines of the respective memory array segment.
A method in a semiconductor memory device for controlling connection of a sense amplifier to, and disconnection from, first and second memory array segments, respectively, comprising:
- a. controlling a first switch or a second switch to disconnect the sense amplifier from the first or second memory array segment, respectively, when the first memory array segment or second memory array segment, respectively, is unselected;
- and
- b. when both the first memory array segment and the second memory array segment are unselected and said second memory array segment has a bitline leakage anomaly, controlling said first switch to connect the sense amplifier to the first memory array segment and controlling said second switch to disconnect the sense amplifier from the second memory array segment for isolating the sense amplifier from the second memory array segment due to the bitline leakage anomaly in the second memory array segment.
A controller for controlling first and second of complementary switch circuits used to connect a sense amplifier to and disconnect a sense amplifier from first and second memory array segments, respectively, of the sense amplifier, the controller comprising:
- a. a control block that receives as input first and second selection signals, first and second isolation control signals and a latch control signal, and comprising a first control path that generates drive state signals for controlling the state of the first switch circuit and a second control path that generates drive state signals for controlling the state of the second switch circuit, wherein the control block is responsive to the first and second selection signals and the first and second isolation control signals, respectively, to generate the drive state signals for the first and second control paths in accordance with a programmable isolation mode to disconnect the sense amplifier from the first memory array segment when the first memory array segment is unselected or to disconnect the sense amplifier from the second memory array segment when the second memory array segment is unselected, and in accordance with a dynamic latch mode to latch the first and second switch circuits to a fixed state during memory access of the first memory array segment or second memory array segment in response to the latch control signal;
- and
- b. a driver block connected to the control block, wherein the driver block comprises a first set of drive circuits responsive to the drive state control signals from the first control path to generate a first switch control signal that puts the first switch circuit into a first state or a second state, and a second set of drive circuits responsive to the drive state control signals from the second control path to generate a second switch control signal that puts the second switching circuit into a first state or a second state.
A controller for first and second complementary switching circuits used to connect a sense amplifier to, and disconnect a sense amplifier from, a first memory array segment and a second memory array segment, respectively, the controller comprising:
- a. first and second control paths for the first and second switching circuits, respectively;
- b. the first control path comprising a programmable isolation control circuit and a dynamic latch circuit, wherein the programmable isolation control circuit in the first control path controls the first switching circuit to disconnect the sense amplifier from the first memory array segment during an unselected state of the first memory array segment and the dynamic latch circuit in the first control path latches the first switching circuit and the second switching circuit to fixed states during access of the first memory array segment or second memory array segment;
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- c. the second control path comprises a programmable isolation control circuit and a dynamic latch circuit, wherein the programmable isolation control circuit controls the second switching circuit to disconnect the sense amplifier from the second memory array segment during an unselected state of the second memory array segment and the dynamic latch circuit in the second control path latches the first switching circuit and the second switching circuit to fixed states during access of the first memory array segment or the second memory array segment.
A controller for a pair of first and second complementary multiplexers in a semiconductor memory device, comprising:
- a. controlling means responsive to selection signals, isolation control signals, and a latch control signal, for generating as output drive state control signals that control the state of first and second multiplexer control signals for the first and second multiplexers, respectively;
- and
- b. driving means connected to the controlling means and responsive to the drive state control signals to generate the first and second multiplexer control signals;
- c. wherein the controlling means is responsive to the isolation control signals to control the driving means to generate a particular state for the first or second multiplexer control signal that causes the first or second multiplexer, respectively, to disconnect a sense amplifier from a first memory array segment or from a second memory array segment, respectively, and wherein the controlling means is responsive to the latch control signal to control the driving means to generate states for the first and second multiplexer control signals that cause the first and second multiplexers to stay in particular states during self-refresh of the first memory array segment or the second memory array segment, respectively.
Dependencies are inferred from the claim text.