Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.
Claims22
A sense amplifier coupled between first and second bit lines in a memory circuit, the sense amplifier comprising:
- cross-coupled first and second inverters coupled between the first and second bit lines, the first and second inverters each having an input and an output;
- and
- means for compensating for a voltage offset between the first bit line and the second bit line associated with at least one mismatch of transistor characteristics between the first and second inverters, including means for capacitively coupling the input of the first inverter to the first bit line and means for capacitively coupling the input of the second inverter to the second bit line.
A sense amplifier coupled between first and second bit lines in a memory circuit, the sense amplifier comprising:
- cross-coupled first and second inverters coupled between the first and second bit lines, the first inverter having an input capacitively coupled to the first bit line and an output directly coupled to the second bit line, the second inverter having an input capacitively coupled to the second bit line and an output directly coupled to the first bit line;
- and
- first and second reset switches each coupled between the input and the output of one of the first and second inverters, the first and second reset switches each adapted to equalize potentials at the input and the output of each of the first and second inverters.
A method for operating a sense amplifier including cross-coupled first and second inverters coupled between the first and second bit lines, the method comprises:
- resetting the first and second inverters, including equalizing potentials at the input and the output of each of the first and second inverters;
- and
- compensating for a voltage offset between the first bit line and the second bit line when the first and second inverters are reset, the voltage offset associated with at least one mismatch of transistor characteristics between the first and second inverters.
A method for operating a sense amplifier including cross-coupled first and second inverters coupled between the first and second bit lines, the method comprises:
- resetting the first and second inverters;
- and
- compensating for a voltage offset between the first bit line and the second bit line by developing voltages across input capacitors when the first and second inverters are reset, the voltage offset associated with at least one mismatch of transistor characteristics between the first and second inverters, the input capacitors each coupled between one of the first and second bit lines and an input of one of the first and second inverters.
A method for operating a sense amplifier including cross-coupled first and second inverters coupled between the first and second bit lines, the method comprises:
- resetting the first and second inverters;
- and
- compensating for a voltage offset between the first bit line and the second bit line when the first and second inverters are reset, including resetting the first and second inverters using an AC-coupled reset path coupled between the first and second bit lines, the voltage offset associated with at least one mismatch of transistor characteristics between the first and second inverters.
Dependencies are inferred from the claim text.