Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.
Claims11
A method for resetting a sense amplifier in preparation for sensing a memory state of a dynamic random access memory (DRAM) cell, the sense amplifier including a first inverter, a first input capacitor coupling a first bit line and an input of the first inverter, a second inverter, and a second input capacitor coupling a second bit line and an input of the second inverter, the method comprising:
- coupling the second bit line to the input of the first inverter to place a potential of the second bit line at the input of the first inverter such that a voltage difference between the first and second bit lines is placed across the first input capacitor;
- and
- coupling the first bit line to the input of the second inverter to place a potential of the first bit line at the input of the second inverter such that a voltage difference between the second and first bit lines is placed across the second input capacitor.
Dependencies are inferred from the claim text.