Semiconductor memory device and method of testing the same
AssigneeElpida Memory, Inc.
InventorMamoru Aoki
Life of this patent
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Abstract
Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept LOW during a precharge period, and activation/deactivation of the two equalizing elements is separately controlled. A failure such as a defect in one of the two equalizing elements subjected to the on/off control by the control signal can be thereby detected.
Claims17
A semiconductor memory device comprising:
- a plurality of equalizing elements, each connected between a pair of bit lines for equalizing said pair of bit lines;
- and
- a control circuit that performs activation/deactivation control of said plurality of equalizing elements, when equalizing said pair of bit lines, wherein when performing a test, control is performed so that activation/deactivation of each of said plurality of equalizing elements is performed separately so that a defective equalizing element may be detected.
A method of testing a semiconductor memory device with a plurality of equalizing elements connected between a pair of bit lines, comprising the steps of:
- performing activation/deactivation control of said plurality of equalizing elements separately, when equalizing;
- and
- detecting a defective equalizing operation.
A semiconductor memory device comprising:
- a plurality of equalizing elements, each connected between a pair of bit lines for equalizing said pair of bit lines;
- a control circuit that performs activation/deactivation control of said plurality of equalizing elements separately, when equalizing said pair of bit lines;
- a sense amplifier shared by first and second memory cell arrays arranged opposed to each other with said sense amplifier interposed therebetween;
- a pair of bit lines on a side of said first memory cell array, connected to a pair of bit lines on a side of said sense amplifier via first transfer gates;
- and
- a pair of bit lines on a side of said second memory cell array, connected to said pair of bit lines on a side of said sense amplifier via second transfer gates;
- wherein
- said plurality of equalizing elements include:
- a first equalizing element that equalizes said pair of bit lines on the side of said first memory cell array;
- and
- a second equalizing element that equalizes said pair of bit lines on the side of said second memory cell array;
- said first and second equalizing elements separately being subjected to activation/deactivation control thereof during a precharge period.
A semiconductor memory device comprising:
- a plurality of equalizing elements, each connected between a pair of bit lines for equalizing said pair of bit lines;
- and
- a control circuit that performs activation/deactivation control of said plurality of equalizing elements separately, when equalizing said pair of bit lines;
- wherein said plurality of equalizing elements include first and second equalizing elements disposed on near-end and far-end sides of said pair of bit lines connected to a sense amplifier, respectively;
- said first and second equalizing elements separately being subjected to activation/deactivation control thereof during a precharge period;
- and
- wherein when performing a test, control is performed so that one of said first and second equalizing elements is activated and the other of said first and second equalizing elements is deactivated.
A semiconductor memory device comprising:
- a plurality of equalizing elements, each connected between a pair of bit lines for equalizing said pair of bit lines;
- and
- a control circuit that performs activation/deactivation control of said plurality of equalizing elements when equalizing said pair of bit lines, wherein when performing a test, control is performed so that one of said plurality of equalizing elements on said pair of bit lines is activated, others of said plurality of equalizing elements remaining deactivated.
Dependencies are inferred from the claim text.