Memory array tester information processing system
AssigneeSpansion LLC
InventorAshot Melik-Martirosian
Life of this patent
Estimating the term…
Abstract
A memory array tester information processing system includes executing a generation block to gather drain currents and gate voltages information for a memory array, utilizing an extraction block to obtain the drain currents and the gate voltages a portion of the memory array and an entire memory array from the generation block or stored information, and executing an analysis block to operate on the drain currents and the gate voltages from the extraction block to correlate operations on the portion of the memory array and the entire memory array. The system includes utilizing a presentation block to format the information used in the analysis block and the results of the analysis block to compute a peak threshold voltage for the memory array.
Claims20
A memory array tester information processing system comprising:
- executing a generation block to gather drain currents and gate voltages information for a memory array;
- utilizing an extraction block to obtain the drain currents and the gate voltages a portion of the memory array and an entire memory array from the generation block or stored information;
- executing an analysis block to operate on the drain currents and the gate voltages from the extraction block to correlate operations on the portion of the memory array and the entire memory array;
- and
- utilizing a presentation block to format the information used in the analysis block and the results of the analysis block to determine a peak threshold voltage for the entire memory array.
A memory array tester information processing system comprising:
- executing a generation block to gather drain currents and gate voltages information for a memory array;
- and
- executing an analysis block to determine an entire memory array peak threshold voltage at 1 μA by an execution of Vt(1 μA)=Vp+ΔVp,1 μA, wherein Vp is a peak subthreshold voltage of the entire memory array and ΔVp,1 μA is the single cell offset between the X-intercept of the natural log of Id and 1 μA Vt.
A memory array tester information processing system comprising:
- generation circuitry to gather drain currents and gate voltages information for a memory array;
- extraction circuitry to obtain the drain currents and the gate voltages a portion of the memory array and an entire memory array from the generation block or stored information;
- analysis circuitry to operate on the drain currents and the gate voltages from the extraction block to correlate operations on the portion of the memory array and the entire memory array;
- and
- presentation circuitry to format the information used in the analysis block and the results of the analysis block to determine a peak threshold voltage for the entire memory array.
A memory array tester information processing system comprising:
- generation circuitry to gather drain currents and gate voltages information for a memory array;
- and
- analysis circuitry for executing an analysis to determine an entire memory array peak threshold voltage at 1 μA by an execution of Vt(1 μA)=Vp+ΔVp,1 μA, wherein Vp is a peak subthreshold voltage of the entire memory array and ΔVp,1 μA is the single cell offset between the X-intercept of the natural log of Id and 1 μA Vt.
Dependencies are inferred from the claim text.