Method and system for improved efficiency of synchronous mirror delays and delay locked loops

A memory device comprising:

• an input terminal that receives a first clock signal having an initial frequency;
• a clock divider that generates a primary modified clock signal having a reduced frequency in comparison with the initial frequency, wherein the primary modified clock signal is generated at least indirectly based upon the first clock signal;
• a delay-locked loop (DLL) that provides a feedback signal;
• a phase detector that is connected at least indirectly to the DLL and to the clock divider, and that receives both the primary modified clock signal and the feedback signal;
• and
• a selector that is coupled at least indirectly to the clock divider, wherein the selector is controlled by the phase detector in order to select a further signal upon which the output signal is based at least indirectly,
• wherein the phase detector determines timing characteristics based upon at least two of the primary modified clock signal, at least one additional modified clock signal, and the feedback signal, wherein the further signal is selected from among the primary modified clock signal and the at least one additional modified clock signal, and wherein the output signal is determined based upon the timing characteristics.

A memory device comprising circuitry to:

• receive a first clock signal having an initial frequency;
• provide a delay signal and a plurality of modified clock signals based upon the first clock signal, each of which has a reduced frequency relative to the initial frequency;
• compare at least one of the modified clock signals with the delay signal;
• select one of the modified clock signals based upon a result of the comparing;
• and
• generate an output signal based at least in part on the selected one of the modified clock signals, wherein the output signal in at least some circumstances is provided by a synchronous mirror delay (SMD).

A memory device comprising circuitry to:

• receive a first clock signal having an initial frequency;
• provide a plurality of modified clock signals based upon the first clock signal, each of which has a reduced frequency relative to the initial frequency;
• compare at least one of the modified clock signals with a feedback signal provided by way of a delay-locked loop (DLL);
• select one of the modified clock signals based upon a result of the comparing;
• and
• generate an output signal based at least indirectly upon the selected one of the modified clock signals.

Circuitry configured to:

• receive a first clock signal having an initial frequency;
• provide a delay signal and a plurality of modified clock signals based upon the first clock signal, each of which has a reduced frequency relative to the initial frequency;
• compare at least one of the modified clock signals with the delay signal;
• select one of the modified clock signals based upon a result of the comparing;
• and
• generate an output signal based at least in part on the selected one of the modified clock signals, wherein the output signal in at least some circumstances is provided by a synchronous mirror delay (SMD).

Circuitry configured to:

• receive a first clock signal having an initial frequency;
• provide a plurality of modified clock signals based upon the first clock signal, each of which has a reduced frequency relative to the initial frequency;
• compare at least one of the modified clock signals with a feedback signal provided by way of a delay-locked loop (DLL);
• select one of the modified clock signals based upon a result of the comparing;
• and
• generate an output signal based at least indirectly upon the selected one of the modified clock signals.

An electronic system comprising:

• a processor;
• and
• an integrated circuit in communication with the processor, wherein the integrated circuit includes
• an input terminal that receives a first clock signal having an initial frequency;
• a clock divider that generates a primary modified clock signal having a reduced frequency in comparison with the initial frequency, wherein the primary modified clock signal is generated at least indirectly based upon the first clock signal;
• a delay-locked loop (DLL) that provides a feedback signal;
• a phase detector that is connected at least indirectly to the DLL and to the clock divider, and that receives both the primary modified clock signal and the feedback signal;
• and
• a selector that is coupled at least indirectly to the clock divider, wherein the selector is controlled by the phase detector in order to select a further signal upon which the output signal is based at least indirectly,
• wherein the phase detector determines timing characteristics based upon at least two of the primary modified clock signal, at least one additional modified clock signal, and the feedback signal, wherein the further signal is selected from among the primary modified clock signal and the at least one additional modified clock signal, and wherein the output signal is determined based upon the timing characteristics.