Data transfer apparatus in semiconductor memory device and method of controlling the same
AssigneeHynix Semiconductor Inc.
InventorsSeung Wook Kwack, Kwan Weon Kim
Life of this patent
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Abstract
Provided is directed to a circuit for controlling data and a data strobe driver in a semiconductor memory device, including: a first delay unit for outputting a data signal with a variable delay; a DQ driver for outputting a data signal according to the data signal passed through the first delay unit and a driver select signal; a second delay unit for outputting a data strobe signal with a variable delay; and a DQS driver for outputting the data strobe signal passed through the second delay unit by being driven according to the driver select signal.
Claims15
A data transfer apparatus in a semiconductor memory device, comprising:
- a DQ pad;
- a DQS pad;
- a first delay unit for adjusting a delay time of a data signal in response to control signals;
- a DQ driver for outputting the data signal outputted from the first delay unit to the DQ pad according to a driver select signal;
- a second delay unit for adjusting a delay time of a data strobe signal in response to the control signals;
- and
- a DQS driver for outputting the data strobe signal outputted from the second delay unit to the DQS pad according to the driver select signal,
- wherein any one of the DQ driver and the DQS driver is activated by the driver select signal, and the driver select signal is generated by one of EMRS control code, MRS control code and test mode code.
A method of controlling the data transfer apparatus in the semiconductor memory device, comprising the steps of:
- providing a plurality of delay paths having different delay times, wherein one of the delay paths is activated by a first control signal;
- adjusting delay times of a data signal and a data strobe signal using the plurality of delay paths, according to the first control signal;
- generating a second control signal for selecting a DQ driver or a DQS driver;
- activating any one of the DQ driver and the DQS driver, according to the second control signal;
- and
- outputting the data signal to a DQ pad through the DQ driver or the data strobe signal to a DQS pad through the DQS driver, according to the second control signal,
- wherein the first and second control signals use one of EMRS code, MRS code and test mode code.
A data transfer apparatus in a semiconductor memory device, comprising:
- a DQ pad;
- a DQS pad;
- a data control means having a plurality of delay paths activated by a first control signal for adjusting delay time of an inputted data signal, the data control means outputting the data signal that the delay time of the data signal is adjusted to the DQ pad according to a second control signal;
- and
- a data strobe control means having a plurality of delay paths activated by the first control signal for adjusting delay time of an inputted data strobe signal, the data strobe control means outputting the data strobe signal to the DQS pad according to the second control signal,
- wherein any one of the data control means and the data strobe control means is activated by the second control signal, and the first and the second control signals are generated by one of EMRS control code, MRS control code and test mode code.
Dependencies are inferred from the claim text.