Register file
AssigneeInternational Business Machines Corporation
InventorsSam Gat-Shang Chu, Saiful Islam, Shelton Siuwah Leung, Jose Angel Paredes
Life of this patent
Estimating the term…
Abstract
A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.
Claims6
A register file comprising:
- a first plurality of cells coupled to a first local bit line;
- a global bit line;
- a first tri-state inverter coupled between the first local bit line and the global bit line, the first tri-state inverter controlled by a first local select signal;
- a second plurality of cells coupled to a second local bit line;
- a second tri-state inverter coupled between the second local bit line and the global bit line, the second tri-state inverter controlled by a second local select signal;
- a latch with its input coupled to the global bit line;
- and
- a third tri-state inverter coupled between an output of the latch and the global bit line, the third tri-state inverter controlled by a hold signal.
A register file comprising:
- a first plurality of cells coupled to a first local bit line;
- a global bit line;
- a first transmission gate coupled between the first local bit line and the global bit line, the first transmission gate controlled by a first local select signal;
- a second plurality of cells coupled to a second local bit line;
- a second transmission gate coupled between the second local bit line and the global bit line, the second transmission gate controlled by a second local select signal;
- a latch with its input coupled to the global bit line;
- and
- a third transmission gate coupled between an output of the latch and the global bit line, the third transmission gate controlled by a hold signal.
Dependencies are inferred from the claim text.