Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb
AssigneeSanDisk Corporation
InventorGeorge Samachisa
Life of this patent
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Abstract
A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.
Claims18
A re-programmable non-volatile memory system, comprising:
- a plurality of memory cells that individually have at least one charge storage element positioned over a channel region between source and drain regions, wherein the source and drain regions are of a first conductivity type within a well of a second conductivity type that is opposite to the first conductivity type, the well being formed within a body of the first conductivity type with a junction therebetween,
- a plurality of control gate lines extending across the charge storage elements of the plurality of memory cells,
- wherein the charge storage elements are formed of a plurality of conductive nanocrystals spatially isolated from one-another, separated from the channel region by a tunnel oxide and separated from the control gate by a dielectric layer,
- a first address decoding and voltage supply circuit connected with the plurality of control gate lines and responsive to an address that applies a programming voltage for a time period to an addressed one of the control gate lines, and
- a second address decoding and voltage supply circuit connected with the source and drain regions that (a) allows the source and drain regions of those of the memory cells along the addressed control gate line that are being programmed to electrically float during the time period that the programming voltage is applied to the addressed control gate line, and (b) connects at least one of the source and drain regions of those of the memory cells along the addressed control gate line that are being inhibited from programming to a voltage source external of the plurality of memory cells during at least a portion of the time period that the programming voltage is applied to the addressed control gate line.
A re-programmable non-volatile memory system, comprising:
- a plurality of memory cells that individually have at least one charge storage element positioned over a channel region between source and drain regions, wherein the source and drain regions are of a first conductivity type within a well of a second conductivity type that is opposite to the first conductivity type, the well being formed within a body of the first conductivity type with a junction therebetween,
- a plurality of control gate lines extending across the charge storage elements of the plurality of memory cells, and
- decoding and voltage supply circuits connectable with the plurality of control gate lines and the source and drain regions in response to a received address that apply a programming voltage to an addressed one of the control gate lines, allow the source and drain regions of memory cells along the addressed control gate line being programmed to electrically float and apply voltages to at least one of the source and drain regions of others of the memory cells along the addressed control gate line not being programmed.
Dependencies are inferred from the claim text.