Method of reducing wordline recovery time

In a memory device having a number of wordlines, a method of substantially reducing an amount of time required for a wordline voltage level (VWL) to reach a pre-determined operating voltage level, comprising:

• selecting one of the wordlines having a wordline capacitance CWL;
• signaling a first switch to connect the selected wordline to a wordline voltage supply through a load capacitance CL at a first node;
• signaling a second switch to disconnect the selected wordline from the wordline voltage supply at a second node in conjunction with the first switch resulting in load capacitance CL being in series with wordline capacitance CWL with respect to the wordline supply voltage;
• applying a wordline charging voltage by the wordline voltage supply at the first node;
• and
• increasing the wordline voltage VWL by charging up a wordline capacitance (CWL) in series with a load capacitance (CL) by way of the applied wordline charging voltage.

A method of rapidly increasing a wordline voltage level VWL of a wordline having a wordline capacitance CWL from an initial wordline voltage level VWLI to a pre-determined target voltage level VWLT, comprising:

• configuring the wordline capacitance CWL and a load capacitance CL in a series configuration with respect to a first node;
• supplying a charging current at the first node;
• charging up the wordline capacitance CWL by way of the charging current thereby increasing the wordline voltage level;
• providing a wordline charging voltage by a wordline voltage supply;
• and
• wherein the first node is connected to the worldline voltage supply in a series configuration by way of a first switch circuit wherein the worldline voltage supply has an initial worldline voltage supply output of approximately 0V which is much more efficient than operating with the initial charge pump output at very high potential;
• and wherein the worldline voltage supply is connected to the wordline capacitance CWL and the load capacitance CL in a parallel configuration at a second node by way of a second switch circuit, wherein the first switch circuit and the second switch circuit act in opposition to each other such that when the first switch is open the second switch is closed, and vice versa.