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US 7,443,734 B2Granted
Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
Estimating the term…
Abstract
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.
Claims18
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- a storage section which stores an initial value of a write voltage corresponding to a write operation and a correction value for correcting the write voltage;
- and a voltage generating circuit which generates a word line write voltage in a first write operation on a first memory cell in the memory cell array or a second write operation on a second memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage stored in the storage section;
- wherein the voltage generating circuit, in the first write operation, generates a first high voltage supplied to the first memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage and further generates voltages higher than the first high voltage in increments of a first step voltage, and in the second write operation, generates a second high voltage supplied to the second memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage and further generates voltages higher than the second high voltage in increments of a second step voltage, and the first step voltage is higher than the second step voltage.
1 more element
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- a storage section which stores an initial value of a write voltage corresponding to a write operation and a correction value for correcting the write voltage;
- and
- a voltage generating circuit which generates a word line write voltage in a first write operation on a first memory cell in the memory cell array or a second write operation on a second memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage stored in the storage section,
- wherein the storage section holds a first voltage value as a difference between a first high voltage and a second high voltage,
- the voltage generating circuit converts the voltage value of the first high voltage into a second voltage value of the greatest common measure of a first step voltage and a second step voltage, obtains a third voltage value by adding the first voltage value and the correction value to the second voltage value, and determines the voltage value of the second high voltage from the third voltage value on the basis of the second step voltage.
3 more elements
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- a storage section which stores an initial value of a write voltage corresponding to the write operation and a correction value for correcting the write voltage, the initial value of the write voltage being trimmed in a die sort test;
- and
- a voltage generating circuit which generates a word line write voltage on the basis of a reference voltage, the initial value and the correction value of the write voltage stored in the storage section in a write operation, and which includes an adjusting circuit that adjusts the reference voltage and that increases the reference voltage as the write voltage increases.
1 more element
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- a control circuit which controls the potentials of the word lines and bit lines;
- a storage section which stores an initial value of a write voltage corresponding to a write operation and a correction value for correcting the write voltage;
- and
- a voltage generating circuit which generates a write voltage based on the initial value of the write voltage and the correction value,
- wherein the control circuit performs a first write operation on the basis of a first write voltage supplied from the voltage generating circuit,
- performs a second write operation on the basis of a voltage a first step voltage higher than the first write voltage supplied from the voltage generating circuit,
- performs an n-th write operation on the basis of a voltage an (n−1)-th step voltage higher than the (n−1)-th write voltage supplied from the voltage generating circuit, and
- performs an (n+1)-th write operation on the basis of a voltage an n-th step voltage higher than the n-th write voltage supplied from the voltage generating circuit, the n-th step voltage satisfying the expression the (n−1)-th step voltage the n-th step voltage.
6 more elements
Dependencies are inferred from the claim text.