High performance flash memory device capable of high density data storage

A memory device comprising:

• at least one away of non-volatile memory cells;
• a voltage supply component configured to generate a programming voltage for simultaneously programming a plurality of the memory cells, the voltage supply component including a DC-to-DC converter;
• and
• control logic configured to simultaneously program the plurality of memory cells, where the plurality of memory cells corresponds to a programming window including a predetermined number of bits to be programmed.

A memory device comprising:

• a core array including at least one array of non-volatile memory cells, the at least one array comprising:
• a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells;
• and
• a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells;
• a plurality of sense amplifiers operatively connected to the plurality of bit lines for sensing a threshold voltage for memory cells connected to the bit lines;
• a voltage supply component configured to generate a programming voltage for simultaneously programming a plurality of the memory cells, the voltage supply component including a DC-to-DC converter;
• control logic configured to receive a programming window containing a predetermined number of bits that are to be programmed in the at least one array, and determine which of the predetermined number of bits are to be programmed in the memory array;
• control logic configured to pre-charge bit lines associated with the predetermined number of bits;
• control logic configured to simultaneously program the predetermined number of bits to corresponding memory cells in the array;
• and
• control logic configured to simultaneously verify a programming state of the predetermined number of bits in the array.

A memory device comprising:

• a core array including at least one array of non-volatile memory cells, the at least one array comprising:
• a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells;
• and
• a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells;
• control logic configured to receive a programming window containing a predetermined number of bits that are to be programmed in the at least one array, and determine which of the predetermined number of bits are to be programmed in the at least one array;
• control logic configured to simultaneously program the predetermined number of bits to corresponding memory cells in the at least one array;
• and
• control logic configured to simultaneously read a programming state of the predetermined number of bits in the at least one array.