Semiconductor nonvolatile memory device
AssigneeRenesas Technology Corp.
InventorsDigh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Abstract
An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
Claims12
An integrated semiconductor nonvolatile memory, comprising:
- a first field effect transistor with a first gate having a gate electrode formed on a semiconductor substrate via an insulating film;
- and
- a second field effect transistor with a second gate electrode formed on the semiconductor substrate via a charge storage film, adjacent to the first field effect transistor;
- wherein programming or erasure is executed by applying a voltage to the second gate electrode and injecting holes from a side of the semiconductor substrate to the charge storage film;
- wherein the programming or erasure is executed by repeating pulse application to the second gate electrode;
- wherein there are a first period and a second period after the first period while the programming or erasure is executed;
- and
- wherein verification voltage is applied to the second gate electrode in the second period and verification voltage is not applied to the second gate electrode in the first period.
An integrated semiconductor nonvolatile memory, comprising:
- a field effect transistor with a gate electrode formed on a semiconductor substrate via a charge storage film;
- wherein programming or erasure is executed by applying a voltage to the gate electrode and injecting holes from a side of the semiconductor substrate to the charge storage film;
- wherein the programming or erasure is executed by repeating pulse application to the gate electrode;
- wherein there are a first period and a second period after the first period while the programming or erasure is executed;
- and
- wherein verification voltage is applied to the gate electrode in the second period and verification voltage is not applied to the gate electrode in the first period.
Dependencies are inferred from the claim text.