NAND flash memory device and method of programming same
AssigneeSamsung Electronic Co., Ltd.
InventorsJin-Wook Lee, Pyung-Moon Zhang
Life of this patent
Estimating the term…
Abstract
Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.
Claims18
A NAND flash memory device, comprising:
- a memory cell array connected to a plurality of bitlines, wherein the plurality of bitlines is divided into N groups of bitlines, where “N” is an integer greater than 2;
- a page buffer storing input data to be programmed in the memory cell array and connected to the memory cell array via the plurality of bitlines;
- and,
- a bitline setup circuit connected to the bitlines and sequentially discharging the N groups of bitlines according to the input data during a single programming operation,
- wherein the bitline setup circuit comprises:
- N switch circuits respectively connecting/disconnecting the N groups of bitlines to/from the page buffer;
- and
- a control circuit controlling operation of the N switch circuits to sequentially discharge the N groups of bitlines through the page buffer.
A NAND flash memory device, comprising:
- a memory cell array comprising a plurality of bitlines divided into an alternating arrangement of even and odd bitlines, wherein the even bitlines are further divided into first, second, and third bitline groups;
- a page buffer storing input data to be programmed in the memory cell array and connected to the plurality of bitlines via a bitline setup circuit, wherein the bitline setup circuit comprises first, second, and third switch circuits connecting the first, second, and third bitline groups, respectively, to the page buffer;
- and
- a control circuit using the first through third switch circuits to sequentially discharge the first through third bitline groups, respectively, in accordance with the input data during a single programming operation.
A method of programming a NAND flash memory device, the method comprising:
- storing input data in a page buffer connected to a memory cell array through a plurality of bitlines, wherein the plurality of bitlines is divided into an alternating arrangement of even and odd bitlines, and wherein the even bitlines are further divided into first, second, and third bitline groups;
- during a single program operation, sequentially setting up bitline voltages for the first through third bitline groups;
- and thereafter,
- applying a program voltage to a selected wordline of the memory cell array.
Dependencies are inferred from the claim text.