Semiconductor integrated device
AssigneeRenesas Technology Corp.
InventorsKenzo Kurotsuchi, Kiyoo Itoh, Norikatsu Takaura, Kenichi Osada
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Abstract
A semiconductor non volatile memory device capable of multiple write operations with high reliability includes memory cells. Each memory cell of the device has a first electrode, a second electrode, and an information storage section between the two electrodes. A segregation of composing elements of the information storage section caused by applying a first current pulse from the first electrode to the second electrode is corrected by applying a second current pulse from the second electrode to the first electrode such that the composition of the storage section recovers to its original state.
Claims22
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current flowing through one of the plurality of bit lines and a second pulse current flowing in a direction opposite to the first pulse current.
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- a plurality of select elements,
- wherein a first pulse current flowing through one of the plurality of bit lines and a second pulse current, which has an amplitude or width different from that of the first pulse current, are provided, said second pulse current flowing in a direction opposite to said first pulse current, and
- an operation to write a first information to one of the plurality of memory cells is executed using at least one of a first pulse combination including said first pulse current with said second pulse current following the first pulse current, and a second pulse combination including said second pulse current and said first pulse current following the second pulse current.
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current having a relatively large amplitude of 50 to 1000 μA flowing through one of the plurality of bit lines and a relatively short pulse width of 5 to 100 ns and a second pulse current having a relatively small amplitude of 20 to 400 μA and a pulse width of 50 to 1000 ns flowing in a direction opposite to the first pulse.
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- plurality of layers adjacent to the information storage sections;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current flowing in a vertical direction to one of the plurality of word lines and a second pulse current flowing in a direction opposite to the first pulse current, and
- the composition of each of said plurality of layers adjacent to the information storage sections is silicon or carbon.
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current flowing through one of the plurality of bit lines, a second pulse current with a smaller current amplitude than that of the first pulse current, and a third pulse current, and
- one of the first pulse current, the second pulse current, and the third pulse current flows in a direction opposite to the others of the first pulse current, the second pulse current, and the third pulse current.
A semiconductor storage device having a plurality of memory cells comprising:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current flowing through one of the plurality of bit lines, and more than one pulse current flowing in a direction opposite to the first pulse current.
A personal computer comprising:
- a semiconductor storage device having a plurality of memory cells and mix mounted with another semiconductor device, wherein the semiconductor storage device includes:
- a plurality of word lines;
- information storage sections mounted on crossing points of the word lines and a plurality of bit lines with an insulating layer in between;
- and
- select elements,
- wherein an operation to write a first information to one of the plurality of memory cells is executed using a first pulse current flowing through one of the plurality of bit lines, and a second pulse current flowing in a direction opposite to the first pulse current.
Dependencies are inferred from the claim text.