Superconducting circuit for high-speed lookup table
AssigneeHypres, Inc.
InventorsAlex F. Kirichenko, Timur V. Filippov, Deepnarayan Gupta
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Abstract
A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
Claims23
A superconducting look up table, comprising:
- a. an address decoder for receiving digital words of a set of digital words;
- and
- b. a memory array, receiving an output from said address decoder, having a row of memory cells for each digital word of said set for providing the contents of said row to an output
- c. in which said address decoder is comprised of a code matching network and signaling logic.
A method for implementing a superconducting look up table, comprising the steps of:
- a. providing an RSFQ address decoder for receiving digital words of a set of digital words;
- b. providing the output of the address decoder to an RSFQ memory array having a row of memory cells for each digital word of said set for providing the contents of said row to an output;
- and
- c. operating both said RSFQ address decoder and said RSFQ memory array to synchronously pipeline input digital words through the address decoder while pipelining corresponding output words from said memory array to an output.
A superconducting look up table, comprising:
- a. an address decoder for receiving digital words of a set of digital words;
- b. a programmable read-only memory array, receiving an output from said address decoder, having a row of memory cells for each digital word of said set for providing the contents of said row to an output;
- c. a readout circuit for the rapid sequential readout of the contents of memory cells corresponding to the sequence of input addresses, while the memory contents remain unchanged;
- and
- d. a memory rewrite circuit for reprogramming the contents of the memory cells with a speed that is substantially slower than the rapid output speed of the memory array.
A method for implementing a superconducting look up table, comprising the steps of:
- a. providing an address decoder for receiving digital words of a set of digital words;
- b. providing a programmable read-only memory array, receiving an output from said address decoder, having a row of memory cells for each digital word of said set for providing the contents of said row to an output;
- c. providing a readout circuit for the rapid sequential readout of the contents of memory cells corresponding to the sequence of input addresses, while the memory contents remain unchanged;
- and
- d. providing a memory rewrite circuit for reprogramming the contents of the memory cells with a speed that is substantially slower than the rapid output speed of the memory array.
Dependencies are inferred from the claim text.