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US 7,443,717 B2Granted
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsMasashi Fujita, Yoshiyuki Kurokawa
Life of this patent
Estimating the term…
Abstract
A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.
Claims16
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a word line connected to gate electrodes of the first transistor and the second transistor;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the first inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the second inverter;
- a fifth transistor connected to the fourth transistor;
- and
- a data line connected to the fifth transistor.
7 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a word line connected to gate electrodes of the first transistor and the second transistor;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the second inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the first inverter;
- a fifth transistor connected to the fourth transistor;
- and
- a data line connected to the fifth transistor.
7 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the first inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the second inverter;
- a fifth transistor connected to the fourth transistor;
- and
- a data line connected to the fifth transistor.
8 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the second inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the first inverter;
- a fifth transistor connected to the fourth transistor;
- and
- a data line connected to the fifth transistor.
8 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a first word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the first inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the second inverter;
- a fifth transistor connected to the fourth transistor;
- a second word line connected to a gate electrode of the fifth transistor;
- and
- a data line connected to the fifth transistor.
9 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a second transistor connected to an input terminal of the second inverter;
- a first word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the second inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the first inverter;
- a fifth transistor connected to the fourth transistor;
- a second word line connected to a gate electrode of the fifth transistor;
- and
- a data line connected to the fifth transistor.
9 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a first data line connected to the first transistor;
- a second transistor connected to an input terminal of the second inverter;
- a second data line connected to the second transistor;
- a first word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the first inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the second inverter;
- a fifth transistor connected to the fourth transistor;
- a second word line connected to a gate electrode of the fifth transistor;
- and
- a third data line connected to the fifth transistor.
11 more elements
A semiconductor device comprising:
- an inverter circuit including a first inverter and a second inverter for holding a data;
- a first transistor connected to an input terminal of the first inverter;
- a first data line connected to the first transistor;
- a second transistor connected to an input terminal of the second inverter;
- a second data line connected to the second transistor;
- a first word line connected to gate electrodes of the first transistor and the second transistor;
- a power supply line connected to the first inverter and the second inverter;
- a ground line connected to the first inverter and the second inverter;
- at least one of a third transistor, a resistor, and a capacitor connected to an output portion of the second inverter and the ground line;
- a fourth transistor connected to the ground line, wherein a gate electrode of the fourth transistor is connected to an output portion of the first inverter;
- a fifth transistor connected to the fourth transistor;
- a second word line connected to a gate electrode of the fifth transistor;
- and
- a third data line connected to the fifth transistor.
11 more elements
Dependencies are inferred from the claim text.