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US 7,443,715 B2Granted
SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.
Claims39
A six transistor SRAM cell, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes;
- wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry;
- and
- wherein the low tunnel barrier intergate insulator includes a metal layer in contact with one of the floating gate and the control gate.
6 more elements
An array of memory cells, comprising:
- a number of SRAM cells, wherein the number of SRAM cells each include a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator includes a metal layer in contact with one of the floating gate and the control gate;
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes;
- a wordline coupled to the pair of access transistors;
- and
- wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry.
6 more elements
An array of six transistor SRAM cells, comprising:
- a number of SRAM cells, wherein the number of SRAM cells each include a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator includes a metal layer in contact with one of the floating gate and the control gate;
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes;
- a wordline coupled to the pair of access transistors;
- and
- wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry.
6 more elements
A six transistor SRAM cell, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes;
- wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry;
- and
- wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
6 more elements
A six transistor SRAM cell, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes;
- and
- wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry;
- wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
6 more elements
A semiconductor structure, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the NMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substance;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a polysilicon control gate having metal disposed thereon that opposes the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al2O3), and wherein the low tunnel barrier intergate insulator includes a further transition metal oxide;
- and
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes.
4 more elements
A semiconductor structure, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the NMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substance;
- a floating gate opposing the channel region and separated therefrom by a gate oxide, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barriel intergate insulator;
- and
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes.
4 more elements
A semiconductor structure, comprising:
- a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the NMOS transistors includes:
- a first source/drain region and a second source/drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region and separated therefrom by a gate oxide;
- and
- a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in
- contact with the low tunnel barrier intergate insulator;
- and
- a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes.
5 more elements
Dependencies are inferred from the claim text.