High-performance memory and related method
AssigneeVIA Technologies, Inc.
InventorChi-Ting Cheng
Life of this patent
Estimating the term…
Abstract
In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging signal and a column selective signal. When the objective memory unit is enabled, the voltage level of the corresponding column line is changed, if the voltage level reaches a threshold voltage level, the auxiliary module enhances the increment of the voltage level of the column line.
Claims10
A memory circuit comprising:
- at least one memory unit arranged in array, each memory unit has a corresponding row line and column line;
- a discharging module connected to the corresponding column line for discharging the column line of an objective memory unit, the discharging module comprising an N-type metal-oxide semi-transistor (NMOS) and an AND gate, wherein the AND gate determines whether to discharge the column line through the NMOS according to a discharging signal and a column selective signal of the column line;
- an auxiliary module connected to the discharging module;
- and
- a sense amplifier connected to the auxiliary module for accessing data stored in the memory unit by detecting an electrical level of the column line of the memory unit;
- wherein the memory circuit discharges the corresponding column line of the objective memory unit according to the discharging signal and the column selective signal;
- wherein when the objective memory unit is enabled, a voltage level of the corresponding column line is changed, and if the voltage level of the corresponding column line reaches a threshold voltage level, the auxiliary module enhances an increment of the voltage level of the column line.
A method of accessing a memory, the memory has a plurality of memory units arranged in array, each memory unit has a corresponding row line and column line, the method comprising:
- decoding and discharging the column line of an objective memory unit;
- decoding the row line of the objective memory unit and enabling the memory unit through the row line to change a voltage level of the column line of the objective memory unit;
- and
- accessing the objective memory unit according to the voltage level of the column line;
- wherein a driving unit is turned on for enhancing an increment of the voltage level of the column line when the voltage level of the column line reaches a threshold voltage level, and the driving unit is turned off when the voltage level of the column line is lower than the threshold voltage level for maintaining the voltage level of the column line.
A memory circuit comprising:
- at least one memory unit arranged in array, each memory unit has a corresponding row line and column line;
- a discharging module connected to the corresponding column line for discharging the column line of an objective memory unit;
- an auxiliary module connected to the discharging module, the auxiliary module comprising a control unit and a driving unit;
- and
- a sense amplifier connected to the auxiliary module for accessing data stored in the memory unit by detecting an electrical level of the column line of the memory unit;
- wherein the memory circuit discharges the corresponding column line of the objective memory unit according to a discharging signal and a column selective signal;
- wherein when the objective memory unit is enabled, a voltage level of the corresponding column line is changed, and if the voltage level of the corresponding column line reaches a threshold voltage level, the auxiliary module enhances an increment of the voltage level of the column line,
- wherein if a transistor is disposed in the memory unit, the control unit turns on the driving unit to enhance the increment of the voltage level of the column line when the voltage level of the column line reaches the threshold voltage level;
- and if there is no transistor disposed in the memory unit, the voltage level of the column line is kept at ground voltage.
Dependencies are inferred from the claim text.