Lowest power mode for a mobile drive
AssigneeMarvell International Ltd.
InventorsRavishanker Krishnamoorthy, Yun Yang, Abdul Elaydi
Life of this patent
Estimating the term…
Abstract
A hard disk drive enters a low power mode to reduce power consumption. To maintain communication with a host device, a communication interface remains energized along with a circuit portion storing configuration data for the communication interface. To energize the communication interface and the circuit portion, low power voltage regulators provide suitable reference voltages. One low power voltage regulator is dedicate to this purpose. Another voltage regulator is converted from an active, switching mode to a low power, linear mode to provide the necessary reference voltage. Also, unique handshaking signals are used to control entry and exit from the low power mode by the hard disk drive.
Claims40
A hard disk drive comprising:
- a logic core to control selection of an operation mode of the hard disk drive, the operation mode including a low power mode and an active mode;
- a communication interface in communication with the logic core;
- and
- a module to generate a first signal and a second signal, the logic core responsive to the first signal to maintain configuration information for the communication interface during the low power mode, the second signal being used to keep the communication interface active during the low power mode.
A hard disk drive comprising:
- means for controlling selection of an operation mode of the hard disk drive, the operation mode including a low power mode and an active mode;
- means for external communication which is in communication with the means for controlling;
- module means for generating a first signal and a second signal, the means for controlling responsive to the first signal to maintain configuration information for the means for external communication during the low power mode, the second signal for keeping the means for external communication active during the low power mode.
A low power method for a hard disk drive, the method comprising:
- engaging the hard disk drive in a low power mode;
- maintaining the availability of configuration information for external communication during the low power mode;
- and
- keeping circuitry to be used for external communication in an active state during the low power mode.
A hard disk drive having a selectable low power mode, the hard disk drive comprising:
- a Universal Serial Bus (USB) interface;
- and
- a system on a chip (SoC) core configured to maintain the availability of configuration data for the USB interface and keep the USB interface in an active state when the hard disk drive is in the low power mode,
- wherein the configuration data is available in the lower power mode as if the hard disk drive is in an active mode.
A hard disk drive having a selectable low power mode, the hard disk drive comprising:
- a Universal Serial Bus (USB) interface;
- and
- system on a chip (SoC) core means for maintaining the availability of configuration data for the USB interface and for keeping the USB interface in an active state when the hard disk drive is in the low power mode,
- wherein the configuration data is available in the low power mode as if the hard disk drive is in an active mode.
A low power mode entry method for a hard disk drive, the method comprising:
- activating an enable signal to enter a low power mode;
- switching a regulator from a switching mode to a linear mode of operation to generate a first regulated signal in the low power mode;
- and
- in response to the first regulated signal, maintaining availability of configuration information for a communication interface to enable external communication with the hard disk drive in the low power mode.
A hard disk drive having a low power mode of operation and an active mode of operation, the hard disk drive comprising:
- a system on a chip (SoC) including
- an SoC core to issue a low power mode entry command to initiate entry to the low power mode from the active mode;
- a Universal Serial Bus (USB) interface in communication with the SoC core;
- a motor controller including
- a first regulator to generate a first signal, the SoC core responsive to the first signal to maintain configuration information for the USB interface during the low power mode, and
- a second regulator to generate a second signal to keep the USB interface active during the low power mode;
- and
- a signal path in communication with the SoC and the motor controller to convey the low power mode entry command from the SoC core to the motor controller.
Dependencies are inferred from the claim text.