US 7,443,432 B2Granted

Suppression of noise in pixel VDD supply

AssigneeDigital Imaging Systems GmbH

InventorTaner Dosluoglu

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Abstract

A circuit and method for correcting for power supply voltage noise using two dummy pixels in each row of pixels of an imager having a number of pixels arranged in rows and columns are described. The dummy pixels are driven by the same power supply as the active pixels but do not have the capability to sense light energy. The first dummy pixel is read at the time the active pixels in a row are reset and stores a signal in a first dummy register related to the voltage level of the power supply at the time the active pixels are reset. The second dummy pixel is read at the time the active pixels in the row are read and stores a signal in a second dummy register related to the voltage level of the power supply at the time the active pixels are read. The signals in the first storage register and second storage register can then be used to correct the signals from the active pixels in the row for the effect of noise caused by power supply voltage level fluctuations.

Claims20

Dependent claims

A pixel array, comprising:

a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and communicates electrically with a power supply;
a first dummy pixel circuit for each said row of active pixel circuits, wherein each said first dummy pixel circuit does not have a photo detector and communicates electrically with said power supply;
a second dummy pixel circuit for each said row of active pixel circuits wherein each said second dummy pixel circuit does not have a photo detector and communicates electrically with said power supply;
a column storage register for each said column of active pixel circuits wherein each said column storage register is connected to all of said active pixel circuits in that said column of active pixel circuits;
a first dummy storage register, wherein each of said first dummy pixel circuits are connected to said first dummy storage register;
a second dummy storage register, wherein each of said second dummy pixel circuits are connected to said second dummy storage register;
a reset line for each of said rows of active pixel circuits wherein one of said reset lines is connected to each said active pixel circuit and said first dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of said pixel circuits selected for reset is reset and said first dummy pixel in said row of active pixel circuits selected for reset stores a signal in said first dummy storage register related to the value of the voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for reset are reset;
a row select line for each of said rows of active pixel circuits wherein one of said row select lines is connected to each said active pixel circuit and said second dummy pixel in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of pixel circuits selected for readout is read and stores a signal in that said column register for the same said column of active pixel circuits and said second dummy pixel in said row of pixel circuits selected for readout stores a signal in said second dummy register related to the value of said voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for readout are read;
means for determining the difference between said signal stored in said first dummy register and said signal stored in said second dummy register;
and
means for correcting said signals stored in each of said column storage registers for fluctuations of said voltage of said power supply using said difference between said signal stored in said first dummy register and said signal stored in said second dummy register.

8 more elements

A method of correcting for noise in a pixel array, comprising:

providing a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and is supplied by a power supply;
providing a first dummy pixel for each row of said active pixel circuits, wherein each said first dummy pixel does not have a photo detector and is supplied by said power supply;
providing a second dummy pixel for each row of said active pixel circuits wherein each said second dummy pixel does not have a photo detector and is supplied by said power supply;
providing a column storage register for each said column of active pixel circuits wherein each said column storage register is connected to each of said active pixel circuits in that said column of pixel circuits;
providing a first dummy storage register wherein said first dummy storage register is connected to each of said first dummy pixels;
providing a second dummy storage register wherein said second dummy storage register is connected to each of said second dummy pixels;
providing a reset line for each of said rows of active pixel circuits wherein one of said reset lines is connected to each said active pixel circuit and said first dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of said pixel circuits selected for reset is reset and said first dummy pixel in said row of pixel circuits selected for reset stores a signal in said first dummy storage register related to the value of the voltage of said power supply at the time said active pixel circuits in said row of active pixel circuits selected for reset are reset;
providing a row select line for each of said rows of active pixel circuits wherein one of said row select lines is connected to each said active pixel circuit and said second dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of pixel circuits selected for readout is read and stores a signal in that said column register for the same said column of active pixel circuits and said second dummy pixel in said row of active pixel circuits selected for readout stores a signal in said second dummy register related to the value of said voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for readout are read;
activating one of said reset lines thereby resetting each of said active pixel circuits in one of said rows of active pixel circuits and storing a signal related to the value of said voltage of said power supply at the time said active pixel circuits in that said row are reset in said first dummy storage register;
activating one of said row select lines thereby reading said active pixel circuits in that said row of active pixel circuits, storing a readout signal in said column registers, and storing a signal related to the value of said voltage of said power supply at the time said active pixel circuits in that said row of active pixel circuits are read in said second dummy register;
and
using the signals stored in said column registers, said first dummy register, and said second dummy register to correct for fluctuations of said voltage of said power supply.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/028,745Filed 4 Jan 2005 · us provisional application
Priority: 15 Jun 2004
Published: US 2005/0275650 A115 Dec 2005
Granted: 28 Oct 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H04N 25/76
SSIS architectures; Circuits associated therewith: addressed sensors, e.g. MOS or CMOS sensors
H04N 25/617
Noise processing, e.g. detecting, correcting, reducing or removing noise: for reducing electromagnetic interference, e.g. clocking noise
H04N
Pictorial communication