Pixel clock spread spectrum modulation
AssigneeNVIDIA Corporation
InventorJonah M. Alben
Life of this patent
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Abstract
Circuits, methods, and apparatus that reduce the peak or maximum EMI generated by video signals provided to a CRT or digital display monitor. One exemplary embodiment provides for spreading the spectrum of the video signal in order to spread or diffuse its peak spectral component. This may be done by spreading the spectrum of a pixel clock that is used to clock or time pixel information provided to the monitor. One embodiment spreads the spectrum of the pixel clock by varying the frequency of its operation. The pixel clock is generated by a phase-locked loop having a number of dividers. These dividers divide the frequency of one or more of the signals around the phase-locked loop. The divide ratio is varied as a function of time, resulting in a variation of an output signal frequency as a function of time.
Claims22
An integrated circuit comprising:
- a phase-locked loop having a divider and configured to provide a pixel clock having a variable frequency;
- and
- an output logic circuit configured to receive the pixel clock and further configured to provide pixel information clocked by the pixel clock,
- wherein the divider is configured to divide a frequency of a signal by a value, and wherein the value is variable over time, and
- wherein the value is determined by entries in a look-up table.
A method of providing a video signal, the method comprising:
- generating a clock signal having a frequency;
- receiving a synchronizing signal;
- varying the clock frequency according to a waveform that is synchronous with a first edge of the synchronizing signal and not synchronous with a second edge of the synchronizing signal such that the clock frequency at the first edge of the synchronizing signal is different from the clock frequency at the second edge of the synchronizing signal;
- and
- providing a plurality of pixels at the clock frequency.
An integrated circuit comprising:
- a clock generating circuit configured to provide a clock signal having a variable frequency, wherein the variable frequency varies in a pattern that repeats each cycle of a first signal, such that the variable frequency has a first value at a first edge of the first signal, a second value at a second edge of the first signal, and a third value at a time between the first edge of the first signal and the second edge of the first signal, the third value different than the first value, and the second value between the first value and the third value;
- an output circuit configured to receive pixel information and provide the pixel information timed to the clock signal;
- and
- a digital-to-analog converter configured to receive the pixel information timed to the clock signal and further configured to provide an analog signal to a monitor.
Dependencies are inferred from the claim text.