Single stage cyclic analog to digital converter with variable resolution

#This disclosure relates generally to Analog-to-Digital (A/D) converters, and more particularly to Redundant Signed Digit (RSD) A/D converters.

#Advances in integrated circuit technology have enabled the development of complex “system-on-a-chip” ICs for a variety of applications such as wireless communications and digital cameras. Such applications are embodied in portable electronic devices for which low power and small circuit area are important design factors. Low power and low voltage circuits are needed to decrease battery power requirements, which can allow for designs that use fewer or smaller batteries, which in turn decreases device size, weight, and operating temperature.

#Such devices, however, receive analog input signals that are typically converted to digital signals. Various conventional cyclic (algorithmic) A/D converters that achieve low power operation and high resolution in a small area are known. For example, U.S. Pat. No. 6,535,157, herein incorporated by reference, discloses a cyclic RSD A/D converter having a single RSD stage followed by a digital logic section that performs synchronization and correction functions.

#The following detailed description of some example embodiments will be better understood when read in conjunction with the appended drawings. It should be understood, however, that example embodiments are not limited to the precise arrangements and instrumentalities shown. In the drawings, like numerals are used to indicate like elements throughout. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

#For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring aspects of the illustrated embodiments. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in some of the figures may be exaggerated relative to other elements or regions of the same or other figures to help improve understanding of the example embodiments. In the drawings:

#FIG. 1 is a simplified schematic block diagram illustrating a conventional single-stage RSD A/D converter;

#The detailed description set forth below in connection with the appended drawings is intended as a description of some of the example embodiments, and is not intended to completely describe all possible embodiments. That is, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description of example embodiments. It is to be understood that the same or equivalent functions may be accomplished by different embodiments.

#The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of use in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises, includes, or has a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

#FIG. 2 is a schematic block diagram of a single-stage RSD A/D converter in accordance with an example embodiment. The A/D converter 200 includes a single multi-bit/single-bit RSD stage 210 and a digital section 220. The digital section 220 has an alignment and synchronization block 230 and a correction block 240. An analog input signal (e.g., voltage) 205 is presented to an input of the single multi-bit/single-bit RSD stage 210 by way of a first switch 212. The RSD stage 210 provides a digital output signal to the digital section 220. The RSD stage 210 also generates a residual voltage signal (VR), which is fed back to the input of the RSD stage by way of the first switch 212. The first switch 212 is closed for the first cycle, in which the analog input signal 205 is received, and then opened for the remaining number of cycles that it takes to complete converting the analog signal to a digital signal. Preferably, the feedback loop of the RSD stage 210 is directly connected from the RSD stage output to the first switch 212, without any intervening circuitry such as a comparator. The number of cycles to complete an A/D conversion of the analog input signal to a digital output signal depends on the number of bits in the digital output signal. The digital bits output from the RSD stage 210 are provided to the digital section 220, where they are aligned, synchronized, and combined to provide a standard format binary output code.