High speed context memory implementation for H.264

An apparatus for decoding a data stream comprising a plurality of video frames that have been encoded using Context-based Adaptive Binary Arithmetic Coding, said apparatus comprising:

• a memory for storing a program;
• and
• a processor for executing the program, said program comprising:
• code for decomposing a current video frame into slices each comprising slice data and slice header information;
• code for storing a context model comprising a plurality of context model values in a manner that enables concurrent processing of a set of the context model values;
• code for identifying a non-bypass slice;
• code for initializing the context model using header information of the identified slice;
• and
• code for decoding the slice data of the identified slice dependent upon the initialized context model.

An apparatus for decoding a data stream comprising a plurality of video frames that have been encoded using Context-based Adaptive Binary Arithmetic Coding, the apparatus comprising:

• means for decomposing a current video frame into slices each comprising slice data and slice header information;
• means for storing a context model comprising a plurality of context model values in a manner that enables concurrent processing of a set of the context model values;
• means for identifying a non-bypass slice;
• means for initializing the context model using header information of the identified slice;
• and
• means for decoding the slice data of the identified slice dependent upon the initialized context model.

A context modeller used in decoding data encoded using Context Adaptive Binary Arithmetic Coding, said context modeler comprising:

• a Read Only Memory for storing uninitialized context model values, said uninitialized context model values being stored in the Read Only Memory in a manner that enables a plurality of uninitialized context model values to be read from the Read Only Memory in a single clock cycle;
• an Arithmetic Logic Module comprising a plurality of parallel processing paths, each said processing path comprising a plurality of pipeline stages;
• a Random Access Memory;
• and
• a memory controller for determining, using the Arithmetic Logic Module operating on said plurality of uninitialized context model values read from the Read Only Memory in each clock cycle, initialized context model values for storage in the Random Access Memory based upon header information in said incoming encoded data.