Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics

A method comprising:

• providing to a phase-locked loop (PLL) circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth;
• generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information;
• and
• storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths, wherein the selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth;
• switching the reference clock signal between a first input clock signal and a second input clock signal while generating the output clock signal having a substantially fixed phase,
• wherein the configuration information includes at least one parameter for adjusting a programmable phase-difference compensation circuit in accordance with the selected frequency of the reference clock signal and the selected PLL bandwidth.

An apparatus comprising:

• a programmable phase-locked loop (PLL) configured to generate an output signal based, at least in part, on a reference clock signal, the PLL having a bandwidth selectable from a range of PLL bandwidths and a frequency of the reference clock signal being selectable from a range of reference clock signal frequencies;
• and
• a first storage circuit configured to provide configuration information to the PLL based, at least in part, on the reference clock signal frequency and the PLL bandwidth,
• wherein the PLL comprises:
• a controllable oscillator circuit;
• and
• a programmable loop filter circuit responsive to a signal based, at least in part, on a phase-difference signal to generate a control signal for the controllable oscillator circuit,
• wherein the configuration information includes parameters for adjusting locations of a zero and higher order poles of the programmable loop filter circuit.

An apparatus comprising:

• a programmable phase-locked loop (PLL) configured to generate an output signal based, at least in part, on a reference clock signal, the PLL having a bandwidth selectable from a range of PLL bandwidths and a frequency of the reference clock signal being selectable from a range of reference clock signal frequencies;
• and
• a first storage circuit configured to provide configuration information to the PLL based, at least in part, on the reference clock signal frequency and the PLL bandwidth,
• wherein the PLL is configured to switch between a first input clock signal and a second input clock signal as the reference clock signal while generating an output signal having a substantially fixed phase,
• wherein the PLL comprises:
• a programmable phase-difference compensation circuit configured to generate a pulsed phase-difference compensation signal in response to the first input clock signal being utilized as the reference clock signal, the first pulsed phase-difference compensation signal being indicative of the phase difference when the second input clock signal was utilized as the reference clock signal prior to the first input clock signal being utilized as the reference clock signal;
• and
• a programmable phase detector and charge pump circuit configured to detect a phase difference between a first feedback signal and a clock signal that corresponds to the first input clock signal and configured to generate a pulsed phase-difference signal indicative thereof,
• wherein the configuration information includes parameters for the phase detector and charge pump circuit.

An apparatus comprising:

• programmable phase-locked loop (PLL) means having a selectable frequency of a reference clock signal and a selectable bandwidth, the programmable PLL means generating an output clock signal based, at least in part, on the reference clock signal and selected configuration parameters;
• means for storing configuration parameters corresponding to a range of frequencies and a range of bandwidths for the PLL;
• and
• means for selecting among the stored configuration parameters according to a selected frequency and a selected bandwidth;
• wherein selected configuration information is provided to the programmable PLL means.