Circuit arrangement for detection of a locking condition for a phase locked loop, and a method

A circuit arrangement for detection of a locking condition for a phase locked loop, comprising:

• a phase locked loop which comprises:
• a phase detector configured to produce a phase signal at an output;
• a charge pump coupled at one input to the output of the phase detector;
• an oscillator coupled at an input to an output of the charge pump, and configured to emit an oscillator signal at the output;
• and
• a frequency divider connected at an input to an output of the oscillator, and at a first output to a first input of the phase detector;
• a counter which comprises:
• an input configured to receive an input signal derived from the phase signal;
• a clock input coupled to the output of the oscillator;
• and
• a connection configured to emit an output signal from the counter as a function of a value which represents the pulse length of the phase signal;
• an evaluation apparatus which comprises a first connection coupled to the connection of the counter, and configured to compare the difference between the pulse lengths of successive pulses with an adjustable limit value D, and
• a logic unit which comprises:
• a first input coupled to the output of the phase detector or to the output ofthe charge pump;
• a second input coupled to a second output of the frequency divider;
• and
• a connection configured to emit an output signal from the logic unit.

A circuit arrangement, comprising:

• a phase locked loop, comprising a phase detector, a charge pump downstream from the phase detector, and an oscillator which is connected downstream from the charge pump and is coupled on the output side to a first input of the phase detector;
• a counter configured to count the cycles of an oscillator signal from the oscillator while a signal derived from a phase signal from the phase detector is at a stable logic level or an approximately stable analog level, and configured to output a pulse length of the phase signal;
• and
• an evaluation apparatus configured to compare at least two differences between the pulse lengths of successive pulses from the counter with an adjustable limit value D.

A method for determination of a locked state of a phase locked loop, comprising:

• determining a first number N of cycles of an oscillator signal from an oscillator while an input signal derived from a phase signal from a phase detector exceeds a first threshold value;
• determining at least two further numbers L, L′ of cycles of the oscillator signal while the input signal exceeds the first threshold value;
• comparing the first number N and the at least two further numbers L, L′ and providing an output signal from an evaluation apparatus having a first value which represents a locked state of the phase locked loop if each of the at least two further numbers L, L′ differs from the first number N by less than an adjustable limit value D, and having a second value which represents a non-locked state of the phase locked loop if one of the at least two further numbers L, L′ differs from the first number N by the adjustable limit value D or by more than the adjustable limit value D;
• or
• determining a second number M of cycles of the oscillator signal while the input signal derived from the phase signal from the phase detector is below a second threshold value;
• determining at least two further numbers K, K′ of cycles of the oscillator signal while the input signal is below the second threshold value;
• comparing the second number M and the at least two further numbers K, K′ and providing an output signal from the evaluation apparatus having a first value which represents a locked state of the phase locked loop if each of the at least two further numbers K, K′ differs from the second number M by less than an adjustable limit value D, and having a second value which represents a non-locked state of the phase locked loop if one of the at least two further numbers K, K′ differs from the second number M by the adjustable limit value D or by more than the adjustable limit value D.

A method for determination of a locked state of a phase locked loop which comprises a phase detector, a charge pump, an oscillator and a frequency divider, comprising:

• supplying a delayed signal which is delayed with respect to a signal which the frequency divider provides during frequency division of an oscillator signal to a logic unit;
• supplying an input signal derived from a phase signal from the phase detector, to the logic unit;
• providing an output signal via the logic unit, the output signal having a first value if the input signal assumes a value which represents the charge pump in a rest state at the time of a pulse of the delayed signal, and having a second value if the input signal assumes a value which represents the charge pump in an active state at the time of a pulse of the delayed signal;
• determining a first number N of cycles of an oscillator signal from the oscillator while the input signal exceeds a first threshold value;
• determining at least one further number L of cycles of the oscillator signal while the input signal exceeds the first threshold value;
• comparing the first number N and the at least one further number L, and producing an output signal, the output signal having a first value which represents a locked state of the phase locked loop if each of the at least one further number L differs from the first number N by less than an adjustable limit value D, and having a second value, which represents a non-locked state of the phase locked loop, if one of the at least one further number L differs from the first number N by the adjustable limit value D or by more than the adjustable limit value D, or
• determining a second number M of cycles of the oscillator signal while the input signal is below a second threshold value;
• determining at least one further number K of cycles of the oscillator signal while the input signal is below the second threshold value;
• comparing the second number M and of the at least one further number K and providing an output signal, the output signal having a first value which represents a locked state of the phase locked loop if each of the at least one further number K differs from the second number M by less than an adjustable limit value D, and having a second value, which represents a non-locked state of the phase locked loop, if one of the at least one further number K differs from the second number M by the adjustable limit value D or by more than the adjustable limit value D.