Active load arrangement

#The present invention relates to an active load arrangement providing proper output load to a device under test.

#Automatic test equipment is frequently employed to run diagnostic tests on integrated circuit devices. A purpose of a testing device is to ensure that integrated circuits under test provide the proper output voltages given the input stimulus of the tester. It is necessary that such devices simulate the proper output load. In the U.S. Pat. No. 4,712,058 is disclosed an active load network for a device under test and for turning on either a current source or a current sink to properly load its output. The current sink and current source each comprises a pair of CMOS transistors connected in series. An active load network that provides low resistance for direct current DC and high impedance for alternating current AC is often necessary when testing an object of for example line interface type. This type of load network prevents superposed AC parameters to be essentially influenced by DC load. When measuring AC parameters of a test object, the AC impedance of the load network must be essentially higher than the AC impedance of the test object. High AC impedance and low DC resistance can be accomplished by an inductance. However, when measuring on low frequency signals from about 200 Hz and high impedance load above 150 kohm is required, the inductance has to be more than 120 H. This type of AC impedance is necessary when measuring for example on line interface circuits within POTS (Plain Old Telephone Service) telephony. A passive inductance i.e. a coil of that inductance size which can stand enough current without being saturated will be bulky and expensive. The necessary size of such a coil may cause other types of problems like magnetic energy storing causing high voltages at circuit breaking or other rapidly changing loads. Also magnetic and electrical EMC problems depending on internal and external crosstalk may occur. Another possible solution would be to design an active inductance. Active inductances have been made with bipolar transistors. Since bipolar transistors are current controlled devices, several are needed in some kind of high current gain configuration like Darlington connection to get the necessary high impedance to the control input of the circuit. Solutions like the one above is however complicated.

#The present invention relates to a problem how to provide proper output load to a device under test requiring low resistance for DC voltages and high impedance for AC voltages.

#FIG. 1 shows a schematic diagram of an active load arrangement connected to a test object.

#FIG. 2 shows an active load arrangement more in detail with the aid of an equivalent MOSFET diagram.

#FIG. 3 shows results from a simulation using the active load arrangement.

#In FIG. 1 is disclosed a test arrangement TA comprising an active load arrangement Z connected to a test object TO. The active load arrangement provides proper output load to the object under test. The test object, which for example can be a POTS line interface circuit in a telecommunication system, comprises an object output O1 and an object input I1. The load arrangement Z comprises an arrangement input I2 associated with the object output O1. The arrangement Z also comprises an arrangement output O2 associated with the object input I1. The load arrangement Z further comprises a MOSFET with a drain D, a gate G and a source S. The semiconductor in this example is of the type IRF610. The drain D is connected to the arrangement input I2. A first resistance R1, in the example 2,2E6 ohm, is connected between the drain D and the gate G. A second resistance R2, in the example 2,2E6 ohm, is connected between the gate G and the source S. A capacitor C1, in the example 6,8 μF, is connected between the gate and the arrangement output O2. An inductance L1, in the example 42 mH, is connected between the source and the arrangement output O2. The inductance L1 is called a first feedback net FBN1 and the resistances R1 and R2 together with the capacitor C1 is called a second feedback net FBN2.

#The test object TO in this example is a POTS line interface circuit and it works under normal OFF HOOK operation with an AC voltage superposed on a DC voltage. In order to activate and measure the AC parameters of the test object, a load arrangement called DC-loop is necessary to supply low-resistance DC load and high-impedance AC load. The low-resistance DC load make the line interface circuit to go into the state where it is working with 2 wire AC voice signals. The high-impedance AC-load is needed because the superposed AC parameters must be as uninfluenced as possible by the DC load. The load arrangement must be essentially higher than the AC impedance of the test object TO.

#The invention will now be explained with the aid of FIG. 1 and FIG. 2. FIG. 2 discloses more in detail the active load arrangement Z shown in FIG. 1. FIG. 2 shows the earlier mentioned first resistance R1, the second resistance R2 and the capacitor C1. In FIG. 2, also the internal resistance RL of the inductance L1 is shown. The MOSFET shown in FIG. 1 is shown in FIG. 2 as an equivalent circuit diagram suitable for simulation of the invention, i.e. a simulation model. A voltage controlled Current Source CS is situated in the MOSFET model between the gate G, the drain D and the source S. A static drain-to-source resistance Rds is shown between drain and source. A reverse transfer capacitance Crss is shown between the gate and the drain. To be able to simulate the approximate DC bias point of the circuit a voltage bias Vbias is placed between the source S and a minus pin of the voltage controlled current source CS.