Thermally stable semiconductor power device
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsSik K Lui, Anup Bhalla, Sanjay Havanur
Life of this patent
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Abstract
A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.
Claims18
A semiconductor power device comprising:
- a circuit for providing a gate driving voltage to a gate of said semiconductor power device wherein said gate driving voltage having a negative temperature coefficient for providing a decreasing gate driving voltage with an increasing temperature whereby the semiconductor power device has a net temperature coefficient less than or equal to zero;
- and
- said semiconductor power device further comprising a trenched MOSFET device with said circuit for providing said gate driving voltage integrated as a first and a second diodes and a first resistor connected in parallel to a source metal and a gate pad and a second resistor connected between an input voltage terminal to said gate pad wherein said first and second diodes and first and second resistors are formed on a polysilicon layer.
A semiconductor power device comprising:
- a circuit for providing a gate driving voltage to a gate of said semiconductor power device wherein said gate driving voltage having a negative temperature coefficient for providing a decreasing gate driving voltage with an increasing temperature whereby the semiconductor power device has a net temperature coefficient less than or equal to zero;
- and
- said semiconductor power device further comprising a planar MOSFET device with said circuit for providing said gate driving voltage integrated as a first and a second diodes and a first resistor connected in parallel to a source metal and a gate pad and a second resistor connected between an input voltage terminal to said gate pad wherein said first and second diodes and first and second resistors are formed on a polysilicon layer.
A method for fabricating a semiconductor power device comprising:
- connecting a circuit for providing a gate driving voltage to a gate of said semiconductor power device with a negative temperature coefficient for providing a decreasing gate driving voltage with an increasing temperature whereby the semiconductor power device has a net temperature coefficient less than or equal to zero;
- and
- said step of fabricating said semiconductor power device further comprising a step of fabricating a trenched MOSFET device with said circuit for providing said gate driving voltage integrated as a first and a second diodes and a first resistor connected in parallel to a source metal and a gate pad and connecting a second resistor between an input voltage terminal to said gate pad by forming said first and second diodes and first and second resistors in a polysilicon layer.
A method for fabricating a semiconductor power device comprising:
- connecting a circuit for providing a gate driving voltage to a gate of said semiconductor power device with a negative temperature coefficient for providing a decreasing gate driving voltage with an increasing temperature whereby the semiconductor power device has a net temperature coefficient less than or equal to zero;
- and
- said step of fabricating said semiconductor power device further comprising a step of fabricating a planar MOSFET device by forming said circuit for providing said gate driving voltage as a first and a second diodes and a first resistor connected in parallel to a source metal and a gate pad and connecting a second resistor between an input voltage terminal to said gate pad by forming said first and second diodes and first and second resistors in a polysilicon layer.
Dependencies are inferred from the claim text.