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US 7,443,222 B1Granted
Dynamic clock control
AssigneeQuickLogic Corporation
InventorsTimothy Saxe, Senani Gunaratna, Stephen U. Yao
Life of this patent
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Abstract
An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.
Claims20
Circuitry to generate a dynamically controlled clock, the circuitry comprising:
- a clock input terminal to couple to a running clock;
- a first input terminal to couple to a first control signal from a programmed antifuse;
- a second input terminal to couple to a second control signal indicative of a switching fabric state;
- an output terminal to provide the dynamically controlled clock;
- a first gate comprising
- a first data input port coupled to the clock input terminal;
- a second data input port;
- and
- a data output port coupled to the output terminal;
- a clock generator comprising
- a clock generator input port coupled to the clock input terminal;
- and
- a clock generator output port to provide an internal clock out-of-phase from the running clock;
- a register comprising
- a register clock input port coupled to the clock generator output port;
- a register data input port coupled to the first input terminal;
- and
- a register data output port coupled to the second data input port of the first gate;
- wherein the second input terminal is coupled to switch a signal to one of the clock generator input port and the register data input port.
16 more elements
A method for generating a dynamically controlled clock, the method comprising:
- providing a running clock;
- providing a first control signal from a programmed antifuse;
- providing a second control signal indicative of a switching fabric state;
- passing, through a multiplexer, the first control signal as a register input data signal to a register data input port of a register, when the second control signal is a first state;
- clocking the register data input signal from the register data input port as a register data output signal to a register data output port;
- feeding back, through the multiplexer, the register data output signal to the register data input port, when the second control signal is a second state;
- and
- combining, at a first gate, the running clock and the register data output signal to generate the dynamically controlled clock.
5 more elements
Circuitry to generate a dynamically controlled clock, the circuitry comprising:
- a clock input terminal to couple to a running clock;
- a first input terminal to couple to a first control signal from a programmed antifuse;
- a second input terminal to couple to a second control signal indicative of a switching fabric state;
- an output terminal to provide the dynamically controlled clock;
- a first gate comprising
- a first data input port coupled to the clock input terminal;
- a second data input port;
- and
- a data output port coupled to the output terminal;
- a clock generator comprising
- a clock generator input port coupled to the clock input terminal;
- and
- a clock generator output port to provide an internal clock out-of-phase from the running clock;
- a register comprising
- a register clock input port coupled to the clock generator output port;
- a register data input port;
- and
- a register data output port;
- a second gate comprising
- a first data input port coupled to the register data output port;
- a second data input port coupled to the second input terminal;
- and
- a data output port coupled to the second data input port of the first gate;
- and
- a multiplexer comprising
- a multiplexer first data input port coupled to the register data output port;
- a multiplexer second data input port coupled to the first input terminal;
- a multiplexer data output port coupled to the register data input port;
- and
- a multiplexer control port coupled to the second input terminal.
27 more elements
Dependencies are inferred from the claim text.