Trimmable delay locked loop circuitry with improved initialization characteristics

A method for initializing a delay locked loop in an integrated circuit having an input clock and an output clock separated by a variable delay line, wherein the loop comprises trim circuitry for adjusting Tac positively or negatively, the method comprising:

• measuring as a first value the progression of a start signal through the variable delay line using a stop signal;
• computing the difference between the first value and a second ideal value, wherein the difference is expressible as a function of both a positive and negative adjustment to Tac;
• adjusting the first value by the difference;
• and
• initializing the variable delay line in accordance with the adjusted first value.

Initialization circuitry for a delay locked loop in an integrated circuit, comprising:

• a variable delay line for receiving an input clock signal;
• a reference delay for receiving the input clock signal;
• a feedback delay for receiving an output of the variable delay line;
• wherein an output of the feedback delay only generates a start signal that progresses through the variable delay line;
• and
• wherein an output of the reference delay only generates a stop signal for capturing the start signal as it progresses through the variable delay line to measure an initial delay for the variable delay line.

Initialization circuitry for a delay locked loop in an integrated circuit, comprising:

• a first delay for receiving an input clock signal;
• a variable delay line for receiving an output of the first delay
• a second delay for receiving an output of the variable delay line, wherein an output of the second delay comprises the output clock signal;
• a delay model coupled between the output of the variable delay line and a feedback delay, wherein the delay model estimates a total delay of the first and second delays;
• a reference delay for receiving the input to the variable delay line;
• a feedback delay for receiving an output of the delay model;
• wherein an output of the feedback delay only generates a start signal that progresses through the variable delay line;
• and
• wherein an output of the reference delay only generates a stop signal for capturing the start signal as it progresses through the variable delay line.