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US 7,443,205 B2Granted
Relatively low standby power
AssigneeMarvell International Ltd.
InventorDavid W. McCarroll
Life of this patent
Estimating the term…
Abstract
Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be maintained in the storage elements.
Claims12
A circuit comprising:
- a first transistor stack coupled between power and ground to receive an input signal from combinational logic and to generate an output signal corresponding to a logical inverse of the input signal, wherein the first transistor stack is further coupled to receive a clock signal and the logical inverse of the clock signal to operate such that transitions of the input signal do not create a direct electrical path between power and ground within the first transistor stack;
- an inverter coupled to receive the output signal from the first transistor stack to generate an output signal corresponding to a logical inverse of the output signal from the first transistor stack;
- a second transistor stack coupled between power and ground to receive the output signal from the inverter and to generate an output signal corresponding to a logical inverse of the signal received from the inverter, wherein the second transistor stack is coupled to receive the clock signal and a logical inverse of the clock signal and to operate such that transitions of the output signal from the inverter do not create a direct electrical path between power and ground within the second transistor stack;
- a logic gate coupled to receive an external clock signal and a standby signal to generate the clock;
- and
- a pass gate that includes first and second pass gate transistors each having a first terminal, a second terminal and a gate terminal, wherein the first terminals are coupled together and receive the output signal, the second terminals are coupled together and output the output signal, a gate terminal of the first pass gate transistor receives the clock signal, and a gate terminal of the second pass gate transistor receives the logical inverse of the clock signal.
3 more elements
A system comprising:
- an omnidirectional antenna;
- and
- a processing device coupled with the antenna, the processing device having:
- a first transistor stack coupled between power and ground to receive an input signal from combinational logic and to generate an output signal corresponding to a logical inverse of the input signal, wherein the first transistor stack is further coupled to receive a clock signal and a logical inverse of the clock signal to operate such that transitions of the input signal do not create a direct electrical path between power and ground within the first transistor stack;
- an inverter coupled to receive the output signal from the first transistor stack to generate an output signal corresponding to a logical inverse of the output signal from the first transistor stack;
- a second transistor stack coupled between power and ground to receive the output signal from the inverter and to generate an output signal corresponding to a logical inverse of the signal received from the inverter, wherein the second transistor stack is coupled to receive the clock signal and the logical inverse of the clock signal and to operate such that transitions of the output signal from the inverter do not create a direct electrical path between power and ground within the second transistor stack;
- a logic gate coupled to receive an external clock signal and a standby signal to generate the clock signal;
- and
- a pass gate that includes first and second pass gate transistors each having a first terminal, a second terminal and a gate terminal, wherein the first terminals are coupled together and receive the output signal, the second terminals are coupled together and output the output signal, a gate terminal of the first pass gate transistor receives the clock signal, and a gate terminal of the second pass gate transistor receives the logical inverse of the clock signal.
6 more elements
Dependencies are inferred from the claim text.