Low leakage and data retention circuitry
AssigneeMosaid Technologies Incorporated
InventorsBarry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Abstract
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
Claims47
An integrated circuit comprising:
- two power supply terminals for powering of the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a Vss ground terminal together defining a range of logic levels;
- cells, each said cells being a selected one of a logic gate and a storage cell, and each said cells including a sleep transistor in series with each electrical connection to one of said power supply terminals;
- generator circuitry for generating a voltage outside said range of logic levels;
- and
- additional circuitry for applying, in a power down mode, said generated voltage to said sleep transistors of said cells.
A storage cell in an integrated circuit, the integrated circuit having a power manager, a Vdd positive supply terminal and a Vss ground supply terminal, the two supply terminals in electrical communication with the storage cell, the storage cell comprising:
- a sleep transistor in series with each electrical connection to one of the supply terminals, said sleep transistor adapted to be turned off by the power manager when in a power down mode;
- and
- a source follower transistor in parallel with said sleep transistor in portions of the storage cell which retain binary data in said power down mode,
- whereby said storage cell stores said binary data.
A storage cell in an integrated circuit, the integrated circuit having a power manager, a Vdd positive supply terminal and a Vss ground supply terminal, the two supply terminals in electrical communication with the storage cell, the storage cell comprising:
- stacked transistors in portions of the storage cell which retain binary data in a power down mode;
- a sleep transistor in series with each electrical connection to one of the supply terminals in remaining portions of the storage call, which are non-retaining portions, and said sleep transistor adapted to be turned off by the power manager when in a power down mode, and
- whereby said storage cell stores said binary data.
A power management method comprising:
- operating an integrated circuit having cells, each of the cells being a selected one of a logic gate and a storage cell, and each of the cells including a sleep transistor in series with each electrical connection to a selected one of a Vdd positive supply terminal and a Vss ground terminal, the Vdd positive supply terminal and the Vss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including:
- generating a voltage outside said range of logic levels;
- and
- applying, in a power down mode, said generated voltage to the sleep transistors of said cells.
Dependencies are inferred from the claim text.